ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet

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Flash MCU family with RAM, E³™ (emulated EEPROM), CAN 2.0B and J1850 BLPD Memories ■ – Internal Memory: Single Voltage Flash up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E ed EEPROM) – In-Application Programming ...

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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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EMULATION CHIP LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... GENERAL DESCRIPTION 1.1 INTRODUCTION The ST92F124/F150/F250 microcontroller is de- veloped and manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance derives from the use of a flexible 256-register programming model for ultra-fast con- text switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 1. ST92F124R9: Architectural Block Diagram FLASH 64 Kbytes Kbyte RAM 2 Kbytes NMI 256 bytes Register File 8/16 bits CPU Interrupt INT[5:0] Management WKUP[13:0] ST9 CORE OSCIN OSCOUT RESET RCCU CLOCK2/8 ...

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Figure 2. ST92F124V1: Architectural Block Diagram FLASH 128 Kbytes Kbyte RAM 4 Kbytes 256 bytes WAIT Register File NMI DS2 8/16 bits RW CPU Interrupt Management INT[6:0] WKUP[15:0] ST9 CORE OSCIN OSCOUT RESET ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 3. ST92F150C(R/V)1/9: Architectural Block Diagram FLASH 128/64 Kbytes Kbyte RAM 2/4 Kbytes 256 bytes WAIT Register File NMI DS2 8/16 bits RW* CPU INT[5:0] Interrupt INT6* Management WKUP[13:0] ...

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Figure 4. ST92F150JDV1: Architectural Block Diagram FLASH 128 Kbytes byte RAM 6 Kbytes 256 bytes WAIT Register File NMI DS2 8/16 bit RW CPU Interrupt INT[6:0] Management WKUP[15:0] ST9 CORE OSCIN OSCOUT RESET ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 5. ST92F250CV2: Architectural Block Diagram FLASH 256 Kbytes byte RAM 8 Kbytes 256 bytes WAIT Register File NMI DS2 8/16 bit RW CPU Interrupt INT[6:0] Management WKUP[15:0] ST9 ...

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PIN DESCRIPTION AS. Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (RW), and Data signals are valid for ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 6. ST92F124R9/R1: Pin Configuration (Top-view LQFP64) WAIT/WKUP5/P5.0 WKUP6/WDOUT/P5.1 SIN/WKUP2/P5.2 WDIN/SOUT/P5.3 TXCLK/CLKOUT/P5.4 RXCL0/WKUP7/P5.5 DCD/WKUP8/P5.6 WKUP9/RTS/P5.7 WKUP4/P4.4 EXTRG/STOUT/P4.5 SDA/P4.6 WKUP1/SCL/P4.7 SS/P3.4 MISO/P3.5 MOSI/P3.6 SCK/WKUP0/P3.7 * Reserved for ST tests, must be left unconnected ** V must be ...

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Figure 7. ST92F124V1: Pin Configuration (Top-view PQFP100) 100 A17/P9.3 1 A18/P9.4 2 A19/P9.5 3 A20/P9.6 4 A21/P9.7 5 WAIT/WKUP5/P5.0 6 WKUP6/WDOUT/P5.1 7 SIN/WKUP2/P5.2 8 WDIN/SOUT/P5.3 9 TXCLK/CLKOUT/P5.4 10 RXCLK/WKUP7/P5.5 11 DCD/WKUP8/P5.6 12 WKUP9/RTS/P5.7 13 ICAPA1/P4.0 14 CLOCK2/P4.1 15 OCMPA1/P4.2 16 ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 8. ST92F124V1: Pin Configuration (Top-view LQFP100) 100 A20/P9.6 A21/P9.7 2 ...

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Figure 9. ST92F150: Pin Configuration (Top-view LQFP64) TX0/WAIT/WKUP5/P5.0 RX0/WKUP6/WDOUT/P5.1 SIN/WKUP2/P5.2 WDIN/SOUT/P5.3 TXCLK/CLKOUT/P5.4 RXCL0/WKUP7/P5.5 DCD/WKUP8/P5.6 WKUP9/RTS/P5.7 WKUP4/P4.4 EXTRG/STOUT/P4.5 SDA/P4.6 WKUP1/SCL/P4.7 SS/P3.4 MISO/P3.5 MOSI/P3.6 SCK/WKUP0/P3.7 * Reserved for ST tests, must be left unconnected ** V must be kept low in standard ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 10. ST92F150C: Pin Configuration (Top-view PQFP100) 100 A17/P9.3 1 A18/P9.4 2 A19/P9.5 3 A20/P9.6 4 A21/P9.7 5 TX0/WAIT/WKUP5/P5.0 6 RX0/WKUP6/WDOUT/P5.1 7 SIN/WKUP2/P5.2 8 WDIN/SOUT/P5.3 9 TXCLK/CLKOUT/P5.4 10 RXCLK/WKUP7/P5.5 11 DCD/WKUP8/P5.6 12 WKUP9/RTS/P5.7 13 ICAPA1/P4.0 14 ...

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Figure 11. ST92F150JD: Pin Configuration (Top-view PQFP100) 100 A17/P9.3 1 A18/P9.4 2 A19/P9.5 3 A20/P9.6 4 A21/P9.7 5 TX0/WAIT/WKUP5/P5.0 6 RX0/WKUP6/WDOUT/P5.1 7 SIN/WKUP2/P5.2 8 WDIN/SOUT/P5.3 9 TXCLK/CLKOUT/P5.4 10 RXCLK/WKUP7/P5.5 11 DCD/WKUP8/P5.6 12 WKUP9/RTS/P5.7 13 ICAPA1/P4.0 14 CLOCK2/P4.1 15 OCMPA1/P4.2 16 ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 12. ST92F150C: Pin Configuration (Top-view LQFP100) 100 A20/P9 A21/P9.7 ...

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Figure 13. ST92F150JD: Pin Configuration (Top-view LQFP100) 100 A20/P9 A21/P9.7 3 TX0/WAIT/WKUP5/P5.0 RX0/WKUP6/WDOUT/P5.1 4 ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Figure 14. ST92F250: Pin Configuration (Top-view PQFP100) 100 SDA1/A17/P9.3 1 SCL1/A18/P9.4 2 A19/P9.5 3 A20/P9.6 4 A21/P9.7 5 TX0/WAIT/WKUP5/P5.0 6 RX0/WKUP6/WDOUT/P5.1 7 SIN/WKUP2/P5.2 8 WDIN/SOUT/P5.3 9 TXCLK/CLKOUT/P5.4 10 RXCLK/WKUP7/P5.5 11 DCD/WKUP8/P5.6 12 WKUP9/RTS/P5.7 13 ICAPA1/P4.0 14 ...

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Figure 15. ST92F250: Pin Configuration (Top-view LQFP100) 100 A20/P9 A21/P9.7 3 TX/WAIT/WKUP5/P5.0 RX/WKUP6/WDOUT/P5.1 4 ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Table 1. ST92F124/F150/F250 Power Supply Pins Name Must be kept low in standard operating mode TEST V REG Stabilization capacitor(s) for internal voltage regulator Table 2. ST92F124/F150/F250 ...

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VOLTAGE REGULATOR The internal Voltage Regulator (VR) is used to power the microcontroller starting from the exter- nal power supply. The VR comprises a Main volt- age regulator and a Low-power regulator. – The Main voltage regulator generates sufficient ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION 1.4 I/O PORTS Port 0, Port 1 and Port 9[7:2] provide the external memory interface. All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels ...

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Note 1: Port 3.0 and Port6 [7:6] present on ST92F250 version only. How to Configure the I/O Ports To configure the I/O ports, use the information in Table 3, Table 4 and the Port Bit Configuration Ta- ble in the ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION 1.5 Alternate Functions for I/O Ports All the ports in the following table are useable for general purpose I/O (input, output or bidirectional). Table 4. I/O Port Alternate Functions Pin No. Port Name LQFP64 PQFP100 LQFP100 ...

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Pin No. Port Name LQFP64 PQFP100 LQFP100 P3 P3.7 16 ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION Pin No. Port Name LQFP64 PQFP100 LQFP100 P6.5 47 ...

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Pin No. Port Name LQFP64 PQFP100 LQFP100 P9.2 - 100 ...

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ST92F124/F150/F250 - GENERAL DESCRIPTION 1.6 OPERATING MODES To optimize the performance versus the power consumption of the device, the ST92F124/F150/ F250 supports different operating modes that can be dynamically selected depending on the per- formance and functionality requirements of the ...

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DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean formats; 14 address- ing ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) Figure 19. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure ...

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MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h and R11100111b represent the ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE 2.3 SYSTEM REGISTERS The System registers are listed in are used to perform all the important system set- tings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a ...

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SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a ...

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SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the number (in the range ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) Figure 22. Pointing to a single group of 16 registers REGISTER GROUP BLOCK NUMBER REGISTER FILE ...

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SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE Note: Setting the HIMP bit is recommended for noise reduction when only internal Memory is used. If the memory access ports are declared as an ad- dress AND as an I/O port (for example: P10... P14 ...

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SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 USER STACK POINTER LOW REGISTER (USPLR) R237 - Read/Write Register Group: E (System) ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE 2.4 MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a ...

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MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers and 2 bits (ENCSR ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE 2.6 ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address ...

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ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three registers are used: CSR, ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0 DPR0 DPR0 DPR0 DPR0 ...

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MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has been executed (or ldpp, ...

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ST92F124/F150/F250 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) Figure 29. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 48/429 9 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh ...

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MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, calls and rets instructions, ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) 3 SINGLE VOLTAGE FLASH & E 3.1 INTRODUCTION The Flash circuitry contains one array divided in two main parts that can each be read independ- ently. The first part contains ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) Figure 31. Flash Memory Structure (Example for 128K Flash device) sense amplifiers 230000h TestFlash 8 Kbytes 231F80h User OTP and Protection registers 000000h Sector F0 8 Kbytes 002000h Sector F1 ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) 3.2 FUNCTIONAL DESCRIPTION 3.2.1 Structure The memory is composed of three parts: – a sector wih the system routines (TestFlash) and the user OTP area – 4 main sectors for ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) FUNCTIONAL DESCRIPTION (Cont’d) Table 9. Memory Structure for 256K Flash device Sector TestFlash (TF) (Reserved) OTP Area Protection Registers (reserved) Flash 0 (F0) Flash 1 (F1) Flash 2 (F2) Flash ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) FUNCTIONAL DESCRIPTION (Cont’d) 3.2.3 Operation The memory has a register interface mapped in memory space (segment 22h). All operations are enabled through the FCR (Flash Control Register ECR ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) Figure 33. Hardware Emulation Flow Emulation Flow Reset Read Status Pages 3 TM Map E in current sector Write operation Yes to complete ? No Write operation Wait for Update ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) 3.3 REGISTER DESCRIPTION 3.3.1 Control Registers FLASH CONTROL REGISTER (FCR) Address: 224000h / 221000h- Read/Write Reset value: 0000 0000 (00h FWMS FPAGE FCHIP FBYTE FSECT ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) REGISTER DESCRIPTION (Cont’d) When in Erase Suspend the memory accepts only the following operations: Read, Erase Resume and Byte Program. Updating the not possible during a Flash Erase Suspend. 0: ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) REGISTER DESCRIPTION (Cont’d) Bit 2 = WFIS: Wait For Interrupt Status. If this bit is reset, the WFI instruction puts the Flash macrocell in Stand-by mode (immediate read possible, but ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) REGISTER DESCRIPTION (Cont’d) The meaning of the FESSx bit for sector x is given in Table 10. Table 10. Sector Status Bits FBUSY FEERR FSUSP EBUSY ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) 3.4 WRITE OPERATION EXAMPLE Each operation (both Flash and by a sequence of instructions like the following: OR FCR, #OPMASK ;Operation selection LD ADD1, #DATA1 ;1st Add and Data LD ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) 3.5 PROTECTION STRATEGY The protection bits are stored in the 4 locations from 231FFCh to 231FFFh (see All the available protections are forced active dur- ing reset, then in the ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) PROTECTION STRATEGY (Cont’d) Bit 2:0 = PWT[2:0]: Password Attempt 2-0. If the TMDIS bit in the NVWPR register (231FFDh) is programmed to 0, every time a Set Protection operation is ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) PROTECTION STRATEGY (Cont’d) NON VOLATILE PASSWORD (NVPWD1-0) Address: 231FFF-231FFEh - Write Only Delivery value: 1111 1111 (FFh PWD7 PWD6 PWD5 PWD4 PWD3 PWD2 PWD1 PWD0 ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) Figure 35. Test /EPB Mode Protection Test/EPB Mode Unprotected Good Password Test/EPB Mode Test/EPB Mode Protected Protected 1st Bad Password Test/EPB Mode Protected Good Password Figure 36. Access Mode Protection ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) Figure 37. WRITE Mode Protection Write Mode Unprotected Reset the Write Protection Bit by a Set Protection Operation Set the Write Protection Bit by a Set Protection Operation executed from ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) 3.6 FLASH IN-SYSTEM PROGRAMMING The Flash memory can be programmed in-system through a serial interface (SCI0). Exiting from reset, the ST9 executes the initializa- tion from the TestFlash code (written ...

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ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & (EMULATED EEPROM) Figure 38. Flash in-system Programming. TestFlash Code Start Initialisation No SOUT0 = 0 ? Jump to Flash Main User Code Internal RAM (User Code Example) Address Yes Match Interrupt (from ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP 4 REGISTER AND MEMORY MAP 4.1 INTRODUCTION The ST92F124/F150/F250 register map, memory map and peripheral options are documented in this section. Use this reference information to sup- plement the functional descriptions given else- where ...

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Figure 39. ST92F150/F250 External Memory Map External Memory SEGMENT 24h 64 Kbytes Segments 20h to 23h (Reserved for internal memory) (256Kbytes) External Memory SEGMENT 4h 64 Kbytes Segments (Reserved for internal memory) (256Kbytes) ST92F124/F150/F250 - REGISTER AND ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Figure 40. ST92F124/F150/F250 TESTFLASH and E SEGMENT 23h SEGMENT 22h 224003h/221000h 224000h/221003h 3 TM FLASH and E Control Registers - 4 bytes mapped in both locations 70/429 Memory Map 64 Kbytes ...

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Figure 41. ST92F124/F150 Internal Memory Map (64K versions) Reserved Area -192 Kbytes SECTOR F2 48 Kbytes SECTOR F1 8 Kbytes SECTOR F0 8 Kbytes ST92F124/F150/F250 - REGISTER AND MEMORY MAP SEGMENT 20h 64 Kbytes 6 Kbytes 4 Kbytes 2 Kbytes ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Figure 42. ST92F124/F150 Internal Memory Map (128K versions) Reserved Area- 128 Kbytes SECTOR Kbytes SECTOR F2 48 Kbytes SECTOR F1 8 Kbytes SECTOR F0 8 Kbytes * Available on ST92F150 versions ...

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Figure 43. ST92F250 Internal Memory Map (256K version) SECTOR F5 64 Kbytes SECTOR F4 64 Kbytes SECTOR F3 64 Kbytes SECTOR F2 48 Kbytes SECTOR F1 8 Kbytes SECTOR F0 8 Kbytes ST92F124/F150/F250 - REGISTER AND MEMORY MAP SEGMENT 20h ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP 4.3 ST92F124/F150/F250 REGISTER MAP Table 16 contains the map of the group F periph- eral pages. The common registers used by each peripheral are listed in Table 15. Be very careful to correctly program ...

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Table 16. Group F Pages Register Map Resources available on the ST92F124/F150/F250 devices: Reg R255 Res R254 Res. R253 R252 R251 Res R250 Res. R249 R248 R247 Res. Res. R246 R245 R244 R243 Res. Res. ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP : Reg R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 Res. R243 R242 R241 R240 * Available on some devices only 76/429 9 Page ...

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Table 17. Detailed Register Map Page Reg. Block No. (Dec) R230 R231 R232 R233 R234 Core R235 R236 R237 N/A R238 R239 R224 R225 I/O R226 Port R227 0:5 R228 R229 R242 R243 R244 INT R245 R246 0 R247 R248 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 I/O Port R241 4 R242 R244 I/O Port R245 5 R246 R248 3 I/O R249 Port R250 6 R251 R252 I/O R253 Port R254 7 R255 R240 R241 ...

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Page Reg. Register Block No. Name (Dec) R240 REG0HR1 R241 REG0LR1 R242 REG1HR1 R243 REG1LR1 R244 CMP0HR1 R245 CMP0LR1 R246 CMP1HR1 R247 CMP1LR1 8 R248 TCR1 R249 TMR1 MFT1 R250 T_ICR1 R251 PRSR1 R252 OACR1 R253 OBCR1 R254 T_FLAGR1 R255 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 11 STIM R242 R243 R240 R241 R242 R243 R244 R245 R246 R247 20 I2C_0 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 MMU R243 ...

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Page Reg. Register Block No. Name (Dec) R240 I2DCCR R241 I2CSR1 R242 I2CSR2 R243 I2CCCR R244 I2COAR1 R245 I2COAR2 R246 I2CDR R247 I2CADR 22 I2C_1* R248 I2CISR R249 I2CIVR R250 I2CRDAP R251 I2CRDC R252 I2CTDAP R253 I2CTDC R254 I2CECCR R255 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 R247 24 SCI-M R248 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 26 SCI-A* R244 R245 R246 R255 ...

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Page Reg. Register Block No. Name (Dec) R240 IC1HR1 R241 IC1LR1 R242 IC2HR1 R243 IC2LR1 R244 CHR1 R245 CLR1 R246 ACHR1 R247 ACLR1 29 EFT1* R248 OC1HR1 R249 OC1LR1 R250 OC2HR1 R251 OC2LR1 R252 CR1_1 R253 CR2_1 R254 SR1 R255 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 CAN1* R247 37 Receive R248 FIFO 0 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 CAN1* ...

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Page Reg. Register Block No. Name (Dec) R240 MCSR R241 MDLC R242 MIDR0 R243 MIDR1 R244 MIDR2 R245 MIDR3 R246 MDAR0 CAN1 * R247 MDAR1 39 Tx R248 MDAR2 Mailbox 0 R249 MDAR3 R250 MDAR4 R251 MDAR5 R252 MDAR6 R253 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 CAN1 * R247 41 Tx R248 Mailbox 2 R249 R250 R251 R252 R253 R254 R255 See “Page Mapping CAN1 * 42 for ...

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Page Reg. Register Block No. Name (Dec) R240 MFMI R241 MDLC R242 MIDR0 R243 MIDR1 R244 MIDR2 R245 MIDR3 R246 MDAR0 CAN0* R247 MDAR1 49 Receive R248 MDAR2 FIFO 0 R249 MDAR3 R250 MDAR4 R251 MDAR5 R252 MDAR6 R253 MDAR7 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 CAN0* R247 51 Tx R248 Mailbox 0 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 CAN0* ...

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Page Reg. Register Block No. Name (Dec) R240 MCSR R241 MDLC R242 MIDR0 R243 MIDR1 R244 MIDR2 R245 MIDR3 R246 MDAR0 CAN0* R247 MDAR1 53 Tx R248 MDAR2 Mailbox 2 R249 MDAR3 R250 MDAR4 R251 MDAR5 R252 MDAR6 R253 MDAR7 ...

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ST92F124/F150/F250 - REGISTER AND MEMORY MAP Page Reg. Block No. (Dec) R240 R241 R242 R243 R244 R245 R246 R247 61 R248 R249 R250 R251 R252 R253 R254 R255 ADC R240 R241 R242 R243 R244 R245 R246 R247 62 R248 R249 ...

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Page Reg. Block No. (Dec) R243 R244 R245 R246 R247 R248 63 ADC R249 R250 R251 R252 R253 R254 R255 Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to ...

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ST92F124/F150/F250 - INTERRUPTS 5 INTERRUPTS 5.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event ...

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The Top Level Interrupt vector is located at ad- dresses 0004h and 0005h in the segment pointed to by the Interrupt Segment Register (ISR external watchdog is used, refer to the Regis- ter and Memory Map section for ...

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ST92F124/F150/F250 - INTERRUPTS 5.3 INTERRUPT PRIORITY LEVELS The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships: – The on-chip peripheral channels and the eight external interrupt sources can be ...

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Figure 45. Example of Dynamic Priority Level Modification in Nested Mode INTERRUPT 6 HAS PRIORITY LEVEL 6 Priority Level CPL is set MAIN program ei INT6 5 MAIN CPL is set to 5 CPL6 > CPL5: ...

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ST92F124/F150/F250 - INTERRUPTS ARBITRATION MODES (Cont’d) Examples In the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. Figure 46. Simple Example of a Sequence ...

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ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, 47), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests with a higher ...

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ST92F124/F150/F250 - INTERRUPTS ARBITRATION MODES (Cont’d) 5.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to ...

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ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – The PC high ...

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ST92F124/F150/F250 - INTERRUPTS 5.6 EXTERNAL INTERRUPTS The ST9 core contains 8 external interrupt sources grouped into four pairs. Table 19. External Interrupt Channel Grouping External Channel Interrupt WKUP[0:15] INTD1 P6[7,5] P5[7:5, 2:0] P4[7,4] INT6 INTD0 INT5 INTC1 INT4 INTC0 INT3 ...

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EXTERNAL INTERRUPTS (Cont’d) Figure 51. External Interrupt Control Bits and Vectors Watchdog/Timer End of count TEA0 INT 0 pin* TEA1 STIM Timer INT 1 pin* TEB0 EFT0 Timer INT 2 pin* TEB1 EFT1 Timer INT 3 pin ...

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ST92F124/F150/F250 - INTERRUPTS 5.7 STANDARD INTERRUPTS (CAN AND SCI-A) The two on-chip CAN peripherals generate 4 inter- rupt sources each. The SCI-A interrupts are mapped on a single interrupt channel. The map- ping is shown in the following table. Table ...

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Figure 53. Standard Interrupt (Channels Control Bits and Vectors ITRX0 ITRX1 ITTX ITSCE CAN_0 * ITRX0 ITRX1 ITTX ITSCE CAN_1 * SCI some devices only ST92F124/F150/F250 - INTERRUPTS ITEE0 ...

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ST92F124/F150/F250 - INTERRUPTS 5.7.2 IMPORTANT NOTE ON STANDARD INTERRUPTS Refer to Section 13.4 on page 5.8 TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to ...

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Figure 54. Top Level Interrupt Structure n WATCHDOG ENABLE WDGEN WATCHDOG TIMER END OF COUNT NMI TLNM TLI IEN n 5.10 INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. ...

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ST92F124/F150/F250 - INTERRUPTS 5.11 INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit ...

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INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit 6 = IPD0: ...

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ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h TLTEV TLIS IAOS EWEN Bits 7:4 = V[7:4]: Most significant nibble of Exter- ...

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INTERRUPT REGISTERS (Cont’d) INTERRUPT MASK REGISTER HIGH (SIMRH) R245 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h Bits 7:1 = Reserved. Bit 0 = IMI0 Channel I Mask bit The IMI0 bit ...

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ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) INTERRUPT PENDING (SIPRL) R250 - Read/Write Register Page: 60 Reset value: 0000 0000 (00h) 7 IPH1 IPH0 IPG1 IPG0 IPF1 Bits 7:0 = IPxx Channel E-H Pending bits The IPxx bits are set by ...

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INTERRUPT REGISTERS (Cont’d) INTERRUPT PRIORITY LEVEL REGISTER LOW (SIPLRL) R253 - Read/Write Register Page: Page 60 Reset Value : 1111 1111 7 PL2H PL1H PL2G PL1G PL2F Bits 7:6 = PL2H, PL1H: INTH0,H1 Priority Level. Bits 5:4 = PL2G, PL1G: ...

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ST92F124/F150/F250 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) Table 25. Standard Interrupt Channel Register map (Page 60) Register Address Name SIMRH R245 Reset value SIMRL IMH1 R246 Reset value SITRH R247 Reset value SITRL ITEH1 R248 Reset value SIPRH R249 Reset value ...

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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) 5.12.1 Introduction The Wake-up/Interrupt Management Unit extends the number of external interrupt lines from (depending on the number of external interrupt lines mapped on external pins of the device). ...

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ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.12.3 Functional Description 5.12.3.1 Interrupt Mode To configure the 16 wake-up lines as interrupt sources, use the following procedure: 1. Configure the mask bits of the 16 wake-up lines (WUMRL, ...

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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) Case 3: NMI = 1 (NMI kept high during the 3rd write instruction of the sequence), bad STOP bit setting sequence The result is the same as Case 1: STOP = 0, EX_STP ...

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ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.12.3.4 NMI Pin Management On the CPU side, if TLTEV=1 (Top Level Trigger Event, bit 3 of register R246, page 0) then a rising edge on the NMI pin will ...

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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.12.4 Programming Considerations The following paragraphs give some guidelines for designing an application program. 5.12.4.1 Procedure for Entering/Exiting STOP mode 1. Program the polarity of the trigger event of external wake-up lines by ...

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ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) 5.12.5 Register Description WAKE-UP CONTROL REGISTER (WUCTRL) R249 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h STOP Bit 2 = STOP: Stop ...

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WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP MASK REGISTER HIGH (WUMRH) R250 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUM15 WUM14 WUM13 WUM12 WUM11 WUM10 WUM9 Bit 7:0 = WUM[15:8]: Wake-Up Mask bits. If WUMx ...

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ST92F124/F150/F250 - INTERRUPTS WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d) WAKE-UP TRIGGER REGISTER (WUTRH) R252 - Read/Write Register Page: 57 Reset Value: 0000 0000 (00h) 7 WUT15 WUT14 WUT13 WUT12 WUT11 WUT10 WUT9 Bit 7:0 = WUT[15:8]: Wake-Up Trigger Polarity ...

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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 6 ON-CHIP DIRECT MEMORY ACCESS (DMA) 6.1 INTRODUCTION The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is ...

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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 6.3 DMA TRANSACTIONS The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations: ...

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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared. To select between using the ISR or the DMASR reg- ister to extend the ...

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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) 6.4 DMA CYCLE TIME The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their ...

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ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 6.6 DMA REGISTERS As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) 7 RESET AND CLOCK CONTROL UNIT (RCCU) 7.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) com- prises two distinct sections: – the Clock Control Unit, which generates and manages the internal ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 60. ST92F124/F150/F250 Clock Distribution Diagram Baud Rate Generator SCK Master 1/N N=2,4,16,32 SCK Slave (Max INTCLK/2) SPI EFTx 1...256 MFTx 1...256 WDG P6.5 1...256 STIM P4.1 CLOCK2/8 P6.0 1/8 DIV2 0 ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.3 CLOCK MANAGEMENT The various programmable features and operating modes of the CCU are handled by four registers: – MODER (Mode Register) This is a System Register (R235, Group E). The input ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 7.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condi- tion), ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 7.3.3 CPU Clock Prescaling The system clock, INTCLK, which may be the out- put of the PLL clock multiplier, CLOCK2, CLOCK2 CK_AF, drives a programmable prescaler which ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 7.3.6 Interrupt Generation System clock selection modifies the CLKCTL and CLK_FLAG registers. The clock control unit generates an external inter- rupt request (INTD0) in the following conditions: – when ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 63. Example of Low Power mode programming in WFI using CK_AF external clock PROGRAM FLOW MX[1:0] ← 00 DX[2:0] ← 000 CSU_CKSEL ← 1 WFI_CKSEL ← 1 XTSTOP ← 1 LPOWFI ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 64. Example of Low Power mode programming in WFI using CLOCK2/16 PROGRAM FLOW MX[1:0] ← 01 DX[2:0] ← 000 CSU_CKSEL ← 1 LPOWFI ← 1 User’s Program WFI instruction WFI status ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.4 CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 *Note: This register contains bits which relate to other ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0110 1000 after a Flash LVD Reset Reset Value: 0100 1000 after a Watchdog Reset Reset Value: ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: 0x00 x111 7 FREEN 0 MX1 MX0 0 Bit 7 = FREEN: PLL Free Running Mode ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 65. RCCU General Timing 20µs External Reset Filtered External Reset CLOCK2 PLL Multiplier clock Internal Reset INTCLK User program execution Boot ROM execution < 4µs Reset phase 20479 x CLOCK1 Exit ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.5 CRYSTAL OSCILLATOR The on-chip components for the crystal oscillator are an inverting circuit, polarised at the trip point. The inverter is built around an n-channel transis- tor, loaded with a current ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) CERAMIC RESONATORS Murata Electronics CERALOCK resonators have been tested with the ST92F150 at 3, 3.68, 4 and 5 MHz. These recommended resonators have built-in capacitors (see The test circuit is shown in ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) 7.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the Reset pin. – A ...

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ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU) RESET/STOP MANAGER (Cont’d) The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDGEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) 8 EXTERNAL MEMORY INTERFACE (EXTMI) 8.1 INTRODUCTION The ST9 External Memory Interface uses two reg- isters (EMR1 and EMR2) to configure external memory accesses. Some interface signals are also affected by WCR - R252 ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) 8.2 EXTERNAL MEMORY SIGNALS The access to external memory is made using the AS, DS, RW, Port 0, Port1, Port9, DS2 and WAIT signals described below. Refer to Figure 76. 8.2.1 AS: Address Strobe ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) 8.2.5 PORT 0 If Port 0 is used as a bit programmable parallel I/O port, it has the same features as a regular port. When set as an Alternate Function, ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Figure 76. External memory Read/Write with a programmable wait NO WAIT CYCLE T1 SYSTEM CLOCK AS (MC=0) ALE (MC=1) (AS pin) P1, P9 ADDRESS DS (MC=0) P0 ADDRESS RW (MC=0) ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Figure 77. Effects of DS2EN on the behavior of DS and DS2 n SYSTEM CLOCK AS (MC=0) ALE (MC=1) DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED): DS (MC=0) DS2 (MC=0) ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) 8.2.8 WAIT: External Memory Wait WAIT (Alternate Function Input, Active low) indi- cates to the ST9 that the external memory requires more time to complete the memory access cycle. If ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) 8.3 REGISTER DESCRIPTION EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h DS2EN ASAF Bit 7 = Reserved. Bit 6 = MC: Mode Control. ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0001 1111 (1Fh ENCSR DPRREM MEMSEL LAS1 LAS0 UAS1 UAS0 Bit 7 = Reserved. ...

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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY INTERFACE REGISTERS (Cont’d) Bit 1:0 = UAS[1:0]: Upper memory address strobe stretch. These two bits contain the number of wait cycles (from add to the System Clock to ...

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I/O PORTS 9.1 INTRODUCTION ST9 devices feature flexible individually program- mable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin alloca- tions. These lines, which are logically grouped as 8-bit ports, can be individually programmed to ...

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ST92F124/F150/F250 - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 ...

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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 80. Control Bits Bit 7 PxC2 PxC27 PxC1 PxC17 PxC0 PxC07 n Table 33. Port Bit Configuration Table ( 1... port number) PXC2n 0 PXC1n 0 PXC0n 0 PXn Configuration ...

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ST92F124/F150/F250 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 81. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 82. Input ...

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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output: (Figure 83) – The Output Buffer is turned Open-drain or Push-pull configuration. – The data stored in the Output Master Latch is copied both into the ...

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ST92F124/F150/F250 - I/O PORTS 9.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 9.5.1 Pin Declared as I/O A pin ...

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ON-CHIP PERIPHERALS 10.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to exter- nal ...

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TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 10.1.2 Functional Description 10.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to page 159. The WDIN Input pin can be used in one of four modes: – Event ...

Page 159

TIMER/WATCHDOG (Cont’d) 10.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input ...

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TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 10.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant and ...

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TIMER/WATCHDOG (Cont’d) 10.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top Level Input ...

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TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 10.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register ...

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TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable. This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: The ...

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STANDARD TIMER (STIM) 10.2 STANDARD TIMER (STIM) 10.2.1 Introduction The Standard Timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes capa- bility. The Standard Timer uses an output (STOUT) pin. ...

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STANDARD TIMER (Cont’d) 10.2.2 Functional Description 10.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the ...

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STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 10.2.4 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW ...

Page 167

EXTENDED FUNCTION TIMER (EFT) 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ...

Page 168

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 91. Timer Block Diagram INTCLK 8 high 8-bit buffer EXEDG 16 BIT 1/2 FREE RUNNING 1/4 COUNTER 1/8 COUNTER ALTERNATE REGISTER CC1 CC0 OVERFLOW EXTCLK DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ...

Page 169

EXTENDED FUNCTION TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MSB At t0 Other instructions Returns the buffered Read LSB At t0 +Dt LSB value at t0 Sequence ...

Page 170

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 92. Counter Timing Diagram, INTCLK divided by 2 INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF Figure 93. Counter Timing Diagram, INTCLK divided by 4 INTCLK INTERNAL RESET TIMER CLOCK ...

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EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.3 Input Capture In this section, the index, i, may The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after ...

Page 172

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 95. Input Capture Block Diagram ICAP1 EDGE DETECT CIRCUIT2 ICAP2 IC2R 16-BIT 16-BIT FREE RUNNING COUNTER Figure 96. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi ...

Page 173

EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.4 Output Compare In this section, the index, i, may This function can be used to control an output waveform or indicating when a period of time has elapsed. When a match ...

Page 174

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Figure 97. Output Compare Block Diagram 16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R OC2R Figure 98. Output Compare Timing Diagram, Internal Clock Divided by 2 OUTPUT COMPARE ...

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EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.5 Forced Compare Mode In this section i may represent The following bits of the CR1 register are used: FOLV2 FOLV1 OLVL2 When the FOLV1 bit is set, the OLVL1 bit is copied ...

Page 176

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) – event occurs on ICAP1 again before the Counter reaches the OC1R value, then the Counter will be reset again and the pulse gener- ated might be longer than expected ...

Page 177

EXTENDED FUNCTION TIMER (Cont’d) 10.3.3.7 Pulse Width Modulation Mode Pulse Width Modulation mode enables the gener- ation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation ...

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EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) – When a write is performed on the CLR or ACLR register in PWM mode, then the Counter will be reset and the pulse-width/period of the waveform generated may not be be ...

Page 179

EXTENDED FUNCTION TIMER (Cont’d) 10.3.4 Interrupt Management The interrupts of the Extended Function Timer are mapped on one of the eight External Interrupt Channels of the microcontroller (refer to the “Inter- rupts” chapter). The three interrupt sources are mapped on ...

Page 180

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) Note: A single access (read/write) to the SR regis- ter at the beginning of the interrupt routine is the first step needed to clear all the EFT interrupt flags second ...

Page 181

EXTENDED FUNCTION TIMER (Cont’d) 10.3.5 Register Description Each Timer is associated with three control and one status registers, and with six pairs of data reg- isters (16-bit values) relating to the two input cap- tures, the two output compares, the ...

Page 182

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) COUNTER HIGH REGISTER (CHR) R244 - Read Only Register Page: 28 Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB ...

Page 183

EXTENDED FUNCTION TIMER (Cont’d) OUTPUT COMPARE 1 (OC1HR) R248 - Read/Write Register Page: 28 Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 ...

Page 184

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) CONTROL REGISTER 1 (CR1) R252 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) 7 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Bit 7 = ICIE Input Capture Interrupt Enable. ...

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EXTENDED FUNCTION TIMER (Cont’d) CONTROL REGISTER 2 (CR2) R253 - Read/Write Register Page: 28 Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 ...

Page 186

EXTENDED FUNCTION TIMER (EFT) EXTENDED FUNCTION TIMER (Cont’d) STATUS REGISTER (SR) R254 - Read Only Register Page: 28 Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ...

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EXTENDED FUNCTION TIMER (Cont’d) Table 37. Extended Function Timer Register Map Address Register 7 Name (Dec.) IC1HR MSB R240 Reset Value IC1LR MSB R241 Reset Value IC2HR MSB R242 Reset Value IC2LR MSB R243 Reset Value CHR MSB R244 Reset ...

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MULTIFUNCTION TIMER (MFT) 10.4 MULTIFUNCTION TIMER (MFT) 10.4.1 Introduction The Multifunction Timer (MFT) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic PWM generation and frequency measurement. The MFT comprises a 16-bit Up/Down counter driven by ...

Page 189

MULTIFUNCTION TIMER (Cont’d) The configuration of each input is programmed in the Input Control Register. Each of the two output pins can be driven from any of three possible sources: – Compare Register 0 logic – Compare Register 1 logic ...

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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.2 Functional Description The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR). 10.4.2.1 Trigger Events A trigger event may be generated by software ...

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MULTIFUNCTION TIMER (Cont’d) 10.4.2.8 Free Running Mode The timer counts continuously ( Down mode) and the counter value simply overflows or underflows through FFFFh or zero; there is no End Of Count condition as such, and no reloading ...

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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Every software or external trigger event on REG0R performs a reload from REG0R resetting the Biload cycle. In One Shot mode (reload initiat software external trigger), reloading is always ...

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MULTIFUNCTION TIMER (Cont’d) 10.4.3 Input Pin Assignment The two external inputs (TxINA and TxINB) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by ...

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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.3.1 TxINA = I/O - TxINB = I/O Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be made only ...

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MULTIFUNCTION TIMER (Cont’d) 10.4.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are ...

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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 10.4.3.13 Autodiscrimination Mode The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and the counter ...

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MULTIFUNCTION TIMER (Cont’d) 10.4.4 Output Pin Assignment Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define the driver for ...

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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF ...

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MULTIFUNCTION TIMER (Cont’d) 10.4.5 Interrupt and DMA 10.4.5.1 Timer Interrupt The timer has 5 different Interrupt sources, be- longing to 3 independent groups, which are as- signed to the following Interrupt vectors: Table 40. Timer Interrupt Structure Interrupt Source COMP ...

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MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Figure 105. Pointer Mapping for Register to Register Transfers Register File 8 bit Counter XXXXXX11 8 bit Addr Pointer XXXXXX10 8 bit Counter XXXXXX01 8 bit Addr Pointer XXXXXX00 10.4.5.4 DMA Transaction Priorities Each ...