ST92F150JDV1QC STMicroelectronics, ST92F150JDV1QC Datasheet - Page 31

• Manufacturer Part Number: ST92F150JDV1QC
• Description: IC MCU 128K FLASH 100-PQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150JDV1QC

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-QFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2137

2 DEVICE ARCHITECTURE
2.1 CORE ARCHITECTURE
The ST9 Core or Central Processing Unit (CPU)
features a highly optimised instruction set, capable
of handling bit, byte (8-bit) and word (16-bit) data,
as well as BCD and Boolean formats; 14 address-
ing modes are available.
Four independent buses are controlled by the
Core: a 16-bit Memory bus, an 8-bit Register data
bus, an 8-bit Register address bus and a 6-bit In-
terrupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
Core.
This multiple bus architecture affords a high de-
gree of pipelining and parallel operation, thus mak-
ing the ST9 family devices highly efficient, both for
numerical calculation, data handling and with re-
gard to communication with on-chip peripheral re-
sources.
2.2 MEMORY SPACES
There are two separate memory spaces:
– The Register File, which comprises 240 8-bit
Figure 18. Single Program and Data Memory Address Space
registers, arranged as 15 groups (Group 0 to E),
each containing sixteen 8-bit registers plus up to
64 pages of 16 registers mapped in Group F,
up to 4 Mbytes
Address
21FFFFh
210000h
20FFFFh
3FFFFFh
3F0000h
3EFFFFh
3E0000h
02FFFFh
020000h
01FFFFh
010000h
00FFFFh
000000h
ST92F124/F150/F250 - DEVICE ARCHITECTURE
Reserved
– A single linear memory space accommodating
2.2.1 Register File
The Register File consists of (see
– 224 general purpose registers (Group 0 to D,
– 6 system registers in the System Group (Group
– Up to 64 pages, depending on device configura-
which hold data and control bits for the on-chip
peripherals and I/Os.
both program and data. All of the physically sep-
arate memory areas, including the internal ROM,
internal RAM and external memory are mapped
in this common address space. The total ad-
dressable memory space of 4 Mbytes (limited by
the size of on-chip memory and the number of
external address pins) is arranged as 64 seg-
ments of 64 Kbytes. Each segment is further
subdivided into four pages of 16 Kbytes, as illus-
trated in
uses a set of pointer registers to address a 22-bit
memory field using 16-bit address-based instruc-
tions.
registers R0 to R223)
E, registers R224 to R239)
tion, each containing up to 16 registers, mapped
to Group F (R240 to R255), see
16K Pages
Data
255
254
253
252
251
250
249
248
247
135
134
133
132
11
10
9
8
7
6
5
4
3
2
1
0
Figure
64K Segments
18. A Memory Management Unit
Code
63
62
33
2
1
0
Figure
Figure
20.
19):
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