MC68HC908SR12CFA Freescale Semiconductor, MC68HC908SR12CFA Datasheet - Page 120

• Manufacturer Part Number: MC68HC908SR12CFA
• Description: MICROCONTROLLER 48 PIN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 31
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1145673

Clock Generator Module (CGM)
8.4.6 Programming the PLL
Data Sheet
120
NOTE:
The following conditions apply when in manual mode:
The following procedure shows how to program the PLL.
The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
2. Choose a practical PLL reference frequency, f
•
•
•
•
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
Before entering tracking mode (ACQ = 1), software must wait a
given time, t
Specifications.), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
Software must wait a given time, t
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
frequency, f
The relationship between f
equation:
where P is the power of two multiplier, and can be 0, 1, 2, or 3
reference clock divider, R. Typically, the reference is 32.768kHz
and R = 1.
Frequency errors to the PLL are corrected at a rate of f
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate.
Clock Generator Module (CGM)
VCLKDES
ACQ
f
VCLK
(See
=
2
; and then solve for the other.
P
8.9 Acquisition/Lock Time
×
f
CGMPCLK
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
BUS
and f
=
AL
2
, after entering tracking mode
VCLK
P
BUSDES
×
4
×
is governed by the
f
BUS
, or the desired VCO
Freescale Semiconductor
RCLK
, and the
RCLK
/R. For