MC68HC908SR12CFA Freescale Semiconductor, MC68HC908SR12CFA Datasheet - Page 247

• Manufacturer Part Number: MC68HC908SR12CFA
• Description: MICROCONTROLLER 48 PIN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 31
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1145673

MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor
Addr.
Addr.
$005A
$005A
$0059
$0059
ADC Data Register High 0
ADC Data Register High 0
ADC Data Register Low 0
ADC Data Register Low 0
Register Name
Register Name
Figure 15-8. ADRH0 and ADRL0 in Left Justified Sign Data Mode
(ADRH0)
(ADRH0)
(ADRL0)
(ADRL0)
Figure 15-7. ADRH0 and ADRL0 in Left Justified Mode
In left justified mode the ADRH0 holds the eight most significant bits
(MSBs), and the ADRL0 holds the two least significant bits (LSBs), of the
10-bit result. The ADRH0 and ADRL0 are updated each time a single
channel ADC conversion completes. Reading ADRH0 latches the
contents of ADRL0. Until ADRL0 is read all subsequent ADC results will
be lost. (See
In left justified sign mode the ADRH0 holds the eight MSBs with the MSB
complemented, and the ADRL0 holds the two least significant bits
(LSBs), of the 10-bit result. The ADRH0 and ADRL0 are updated each
time a single channel ADC conversion completes. Reading ADRH0
latches the contents of ADRL0. Until ADRL0 is read all subsequent ADC
results will be lost. (See
Justified Sign Data
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
Bit 7
AD9
AD1
AD9
AD1
Analog-to-Digital Converter (ADC)
R
R
R
R
0
0
0
0
Figure 15-7 . ADRH0 and ADRL0 in Left Justified
AD8
AD0
AD8
AD0
R
R
R
R
6
0
0
6
0
0
Mode.)
Figure 15-8 . ADRH0 and ADRL0 in Left
AD7
AD7
R
R
R
R
5
0
0
0
5
0
0
0
AD6
AD6
R
R
R
R
4
0
0
0
4
0
0
0
AD5
AD5
R
R
R
R
3
0
0
0
3
0
0
0
Analog-to-Digital Converter (ADC)
AD4
AD4
R
R
R
R
2
0
0
0
2
0
0
0
AD3
AD3
R
R
R
R
1
0
0
0
1
0
0
0
I/O Registers
Data Sheet
Mode.)
Bit 0
Bit 0
AD2
AD2
R
R
R
R
0
0
0
0
0
0
247