MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 100

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MC68HC705JP7CDW

Manufacturer Part Number
MC68HC705JP7CDW
Description
IC MCU 8BIT 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705JP7CDW

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
22
Program Memory Size
6KB (6K x 8)
Program Memory Type
OTP
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Simple Synchronous Serial Interface
9.3.3 SIOP Data Register
The SIOP data register (SDR) is located at address $000C and serves as both the transmit and receive
data register. Writing to this register will initiate a message transmission if the node is in master mode.
The SIOP subsystem is not double buffered and any write to this register will destroy the previous
contents. The SDR can be read at any time. However, if a transfer is in progress the results may be
ambiguous. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted
and/or received.
reset.
100
Address:
Reset:
Read:
Write:
Figure 9-6
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$000C
Bit 7
Bit 7
shows the position of each bit in the register. This register is not affected by
Figure 9-6. SIOP Data Register (SDR)
6
6
5
5
Unaffected by reset
4
4
3
3
2
2
1
1
Freescale Semiconductor
Bit 0
Bit 0

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