MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 113

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

IEDG — Input Capture Edge Select
OLVL — Output Compare Output Level Select
11.7 Timer Status Register
The timer status register (TSR) shown in
Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits
in the TSR.
ICF — Input Capture Flag
OCF — Output Compare Flag
Freescale Semiconductor
The state of this read/write bit determines whether a positive or negative transition triggers a transfer
of the contents of the timer register to the input capture register. This transfer can occur due to
transitions on the TCAP pin or the CPF2 flag bit of voltage comparator 2. Resets have no effect on the
IEDG bit.
The state of this read/write bit determines whether a logic 1 or a logic 0 is transferred to the TCMP pin
when a successful output compare occurs. Reset clears the OLVL bit.
•
•
•
The ICF bit is automatically set when an edge of the selected polarity occurs on the TCAP pin. Clear
the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL,
$0015) of the input capture registers. Resets have no effect on ICF.
The OCF bit is automatically set when the value of the timer registers matches the contents of the
output compare registers. Clear the OCF bit by reading the timer status register with the OCF set and
then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on
OCF.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
1 = Signal to TCMP pin goes high on output compare.
0 = Signal to TCMP pin goes low on output compare.
An active signal on the TCAP pin or the CPF2 flag bit of voltage comparator 2 in the analog
subsystem, transferring the contents of the timer registers to the input capture registers
A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to
the PB4/AN4/TCMP pin if that pin is set as an output
An overflow of the timer registers from $FFFF to $0000
Address:
The IEDG bit must be set when either mode 2 or 3 of the analog subsystem
is being used for A/D conversions. Otherwise, the input capture will not
occur on the rising edge of the comparator 2 flag.
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$0013
Bit 7
ICF
U
Figure 11-11. Timer Status Register (TSR)
= Unimplemented
OCF
U
6
Figure 11-11
TOF
U
5
NOTE
4
0
0
contains flags for these events:
U = Unaffected
3
0
0
2
0
0
1
0
0
Timer Status Register
Bit 0
0
0
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