MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 44

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Resets
5.2 Power-On Reset
A positive transition on the V
conditions during powering up and cannot be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (t
generator to stabilize. If the RESET pin is at logic 0 at the end of this multiple t
in the reset condition until the signal on the RESET pin goes to a logic 1.
5.3 External Reset
A logic 0 applied to the RESET pin for a minimum of one and one half t
This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is
pulled below the lower threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown device that is activated by three
internal reset sources. This reset pulldown device will only be asserted for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
5.4 Internal Resets
The four internally generated resets are:
Only the COP watchdog timer reset, low-voltage reset, and illegal address detector will also assert the
pulldown device on the RESET pin for the duration of the reset function or for three to four internal bus
cycles, whichever is longer.
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly
for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out); that
function can be performed by the LVR. Depending on the DELAY bit in the mask option register (MOR),
there is an oscillator stabilization delay of 16 or 4064 internal bus cycles after the LPO becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the
end of the 16- or 4064-cycle delay, the RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. V
POR circuit to detect the next rise of V
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Initial power-on reset (POR) function
COP watchdog timer reset
Low-voltage reset (LVR)
Illegal address detector
Do not connect the RESET pin directly to V
power supply designs if the internal pulldown on the RESET pin should
activate. If an external reset function is not required, the RESET pin should
be left unconnected.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
DD
pin generates a power-on reset. The power-on reset is strictly for
DD
.
cyc
) after the oscillator becomes active allows the clock
NOTE
DD
, as this may overload some
DD
must drop below V
cyc
generates an external reset.
cyc
time, the MCU remains
Freescale Semiconductor
POR
for the internal