MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 41

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MC68HC705JP7CDW

Manufacturer Part Number
MC68HC705JP7CDW
Description
IC MCU 8BIT 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705JP7CDW

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, Temp Sensor, WDT
Number Of I /o
22
Program Memory Size
6KB (6K x 8)
Program Memory Type
OTP
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
4.9 Analog Interrupts
The analog subsystem can generate the following interrupts:
Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these
interrupts are in the analog subsystem control register (ACR) located at $001D, and the status bits are in
the analog subsystem status register (ASR) located at $001E.
4.9.1 Comparator Input Match Interrupt
A comparator input match interrupt occurs if either compare flag bit (CPF1 or CPF2) in the ASR becomes
set while the comparator interrupt enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits
can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits in the ASR. Reset clears these
bits.
4.9.2 Input Capture Interrupt
The analog subsystem can also generate an input capture interrupt through the 16-bit programmable
timer. The input capture can be triggered when there is a match in the input conditions for the voltage
comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the input capture enable (ICEN) in
the ACR is set, then an input capture will be performed by the programmable timer. If the ICIE enable bit
in the TCR is also set, then an input compare interrupt will occur. Reset clears these bits.
Freescale Semiconductor
Voltage on positive input of comparator 1 is greater than the voltage on the negative input of
comparator 1.
Voltage on positive input of comparator 2 is greater than the voltage on the negative input of
comparator 2.
Trigger of the input capture interrupt from the programmable timer as described in
Capture Interrupt
For the analog subsystem to generate an interrupt using the input capture
function of the programmable timer, the ICEN enable bit in the ACR, and
the ICIE and IEDG bits in the TCR must all be set.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
NOTE
Analog Interrupts
4.7.1 Input
41

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