MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 36

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Interrupts
4.4 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
4.5 External Interrupts
These sources can generate external interrupts:
Setting the I bit in the condition code register or clearing the IRQE bit in the interrupt status and control
register disables these external interrupts.
4.5.1 IRQ/V
An interrupt signal on the IRQ/V
the input from the IRQ/V
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit is clear and the
IRQE bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches
the interrupt vector, so that another external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new
interrupt request.
The IRQ/V
interrupt sensitivity is programmed with the LEVEL bit in the mask option register (MOR).
With the edge- and level-sensitive trigger MOR option, a falling edge or a low level on the IRQ/V
latches an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection
to the IRQ/V
an external interrupt request is present, and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the IRQ/V
request. A subsequent interrupt request can be latched only after the voltage level on the IRQ/V
returns to a logic 1 and then falls again to logic 0.
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•
•
IRQ/V
PA3–PA0 pins
PP
PP
PP
pin can be negative edge-triggered only or negative edge- and low level-triggered. External
PP
If the IRQ/V
The response of the IRQ/V
capability of the PA0 through PA3 pins is enabled. If the port A pins are
enabled as external interrupts, then any high level on a PA0–PA3 pin will
cause the IRQ changes and state to be ignored until all of the PA0–PA3
pins have returned to a low level.
pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ low,
pin
Pin
Figure 4-3
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
PP
PP
pin is processed by a Schmitt trigger gate. When the CPU completes its
shows the logic for external interrupts.
pin is not in use, it should be connected to the V
PP
pin latches an external interrupt request. To help clean up slow edges,
PP
pin can be affected if the external interrupt
NOTE
NOTE
PP
pin latches an external interrupt
DD
pin.
Freescale Semiconductor
PP
PP
pin
pin