MC68HC908JB8JDW Freescale Semiconductor, MC68HC908JB8JDW Datasheet - Page 110

• Manufacturer Part Number: MC68HC908JB8JDW
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

System Integration Module (SIM)
8.6.5 Status Flag Protection in Break Mode
8.7 Low-Power Modes
8.7.1 Wait Mode
Technical Data
110
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism — for example, a read of
one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
Executing the WAIT or STOP instruction puts the MCU in a low-power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
here. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
System Integration Module (SIM)
Figure 8-13
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
shows the timing for wait mode entry.
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