MC68HC908JB8JDW Freescale Semiconductor, MC68HC908JB8JDW Datasheet - Page 223

• Manufacturer Part Number: MC68HC908JB8JDW
• Description: IC MCU 8K FLASH 3MHZ 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

13.6 PTE4/D– Pin
13.7 IRQ Module During Break Interrupts
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
NOTE:
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
An internal pullup resistor to V
disabled by setting the IRQPD bit in the IRQ option control register
($001C).
The PTE4 pin is configured as an interrupt input to trigger the IRQ
interrupt when the following conditions are satisfied:
Setting PTE4IE configures the PTE4 pin to an input pin with an internal
pullup device. The PTE4 interrupt is "ORed" with the IRQ input to trigger
the IRQ interrupt (see
Therefore, the IRQ status and control register affects both the IRQ pin
and the PTE pin. An interrupt on PTE4 also sets the PTE4 interrupt flag,
PTE4IF, in the IRQ option control register (IOCR).
The system integration module (SIM) controls whether the IRQ latch can
be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear the latches during the break
state. (See
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
•
•
The USB module is disabled (USBEN = 0)
PTE4 pin configured for external interrupt input (PTE4IE = 1)
Section 8. System Integration Module
External Interrupt (IRQ)
Figure 13-1 . IRQ Module Block
DD
is connected to IRQ pin; this can be
External Interrupt (IRQ)
(SIM).)
Diagram).
Technical Data
PTE4/D– Pin
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