MC68HC908JB8JDW Freescale Semiconductor, MC68HC908JB8JDW Datasheet - Page 203

IC MCU 8K FLASH 3MHZ 20-SOIC

MC68HC908JB8JDW

Manufacturer Part Number
MC68HC908JB8JDW
Description
IC MCU 8K FLASH 3MHZ 20-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908JB8JDW

Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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12.3.2 Data Direction Register A
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
* DDRA7 bit is reset by POR or LVI reset only.
Address:
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4
Reset:
Read:
Write:
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
$0004
Bit 7
0*
Figure 12-3. Data Direction Register A (DDRA)
shows the port A I/O logic.
Input/Output Ports (I/O)
DDRA6
6
0
Figure 12-4. Port A I/O Circuit
RESET
DDRA5
0
5
DDRA4
DDRAx
0
4
PTAx
DDRA3
0
3
DDRA2
0
2
Input/Output Ports (I/O)
DDRA1
1
0
Technical Data
DDRA0
Bit 0
Port A
0
PTAx
203

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