MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 119

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 12-4
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Freescale Semiconductor
PTAPUE Bit
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V
X
1
0
shows the port A I/O logic.
Address:
Reset:
Read:
Write:
DDRA Bit
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
0
0
1
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
PTAPUE7
PTAPUEx
$000D
Bit 7
DD
0
by internal pullup device
PTA Bit
PTAPUE6
X
X
X
(1)
6
0
Table 12-2. Port A Pin Functions
RESET
MC68HC908GP32 Data Sheet, Rev. 10
Figure 12-4. Port A I/O Circuit
V
PTAPUE5
I/O Pin Mode
DD
Input, Hi-Z
Input, V
INTERNAL
PULLUP
DEVICE
5
0
Output
Table 12-2
DD
PTAPUE4
DDRAx
(4)
(2)
PTAx
4
0
Accesses to DDRA
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
PTAPUE3
summarizes the operation of the port A pins.
Read/Write
3
0
PTAPUE2
2
0
PTA7–PTA0
PTAPUE1
Read
1
0
Pin
Pin
Accesses to PTA
PTAPUE0
Bit 0
PTAx
0
PTA7–PTA0
PTA7–PTA0
PTA7–PTA0
Write
Port A
(3)
(3)
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