MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 181

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SPSCK. This uncertainty causes the variation in the initiation delay shown in
no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
15.6 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready
Freescale Semiconductor
SPSCK CYCLE
CPHA = 1
CPHA = 0
NUMBER
CLOCK
SPSCK
SPSCK
CLOCK
CLOCK
CLOCK
CLOCK
MOSI
BUS
BUS
BUS
BUS
BUS
Figure 15-7. Transmission Start Delay (Master)
TO SPDR
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
TO SPDR
WRITE
WRITE
EARLIEST
EARLIEST
EARLIEST
EARLIEST
MC68HC908GP32 Data Sheet, Rev. 10
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
LATEST
SPSCK = INTERNAL CLOCK ÷ 128;
SPSCK = INTERNAL CLOCK ÷ 32;
SPSCK = INTERNAL CLOCK ÷ 8;
128 POSSIBLE START POINTS
32 POSSIBLE START POINTS
8 POSSIBLE START POINTS
SPSCK = INTERNAL CLOCK ÷ 2;
INITIATION DELAY
2 POSSIBLE START POINTS
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
Figure
Queuing Transmission Data
BIT 5
3
15-7. This delay is
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