MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 176

• Manufacturer Part Number: MC68HC908GP32CB
• Description: IC MCU 32K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface Module (SPI)
15.4 Functional Description
Figure 15-1
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. (See
12.4.3 Port C Input Pullup Enable
The following paragraphs describe the operation of the SPI module.
15.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. (See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
176
Addr.
$0010 SPI Control Register (SPCR)
$0011
$0012
15.13.2 SPI Status and Control
Register Name
SPI Status and Control
summarizes the SPI I/O registers and
Register (SPSCR)
SPI Data Register
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See
(SPDR)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 15-1. SPI I/O Register Summary
Register.)
SPRIE
Bit 7
SPRF
MC68HC908GP32 Data Sheet, Rev. 10
R7
T7
0
0
Register.) Through the SPSCK pin, the baud rate generator of the
= Unimplemented
ERRIE
R6
T6
6
R
Figure
0
0
NOTE
Figure 15-2
SPMSTR
15-3.)
OVRF
15.13.1 SPI Control
R5
T5
5
1
0
Unaffected by reset
MODF
CPOL
shows the structure of the SPI module.
R4
T4
R
4
0
0
CPHA
SPTE
R3
T3
3
1
1
= Reserved
Register.)
MODFEN
SPWOM
R2
T2
2
0
0
Freescale Semiconductor
SPR1
SPE
R1
T1
1
0
0
SPTIE
Bit 0
SPR0
R0
T0
0
0