MC68HC908GP32CB Freescale Semiconductor, MC68HC908GP32CB Datasheet - Page 33

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MC68HC908GP32CB

Manufacturer Part Number
MC68HC908GP32CB
Description
IC MCU 32K FLASH 8MHZ 42-SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GP32CB

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Freescale Semiconductor
† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Addr.
$001D
$001E
$001F
$002A
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
Timer 1 Channel 0 Status and
Timer 1 Channel 1 Status and
Timer 1 Status and Control
Timer 1 Counter Modulo
Control Register (T1SC0)
Control Register (T1SC1)
Register Name
Configuration Register 2
Configuration Register 1
Timer 1 Counter Modulo
IRQ Status and Control
Timer 1 Channel 0
Timer 1 Channel 0
Timer 1 Channel 1
Timer 1 Channel 1
Timer 1 Counter
Timer 1 Counter
Register Low
Register High
Register High
Register High
Register High
Register Low
Register Low
Register Low
(CONFIG2)†
(CONFIG1)
(T1MODL)
(T1MODH)
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
(T1CNTH)
(T1CH0H)
(T1CH1H)
(T1CNTL)
(INTSCR)
(T1CH0L)
(T1CH1L)
Register
Register
(T1SC)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
COPRS
Bit 7
Bit 15
Bit 15
CH0F
Bit 15
CH1F
Bit 15
MC68HC908GP32 Data Sheet, Rev. 10
TOF
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
= Unimplemented
LVISTOP
CH0IE
CH1IE
TOIE
14
14
14
14
6
0
0
0
0
0
0
0
6
0
1
6
1
0
6
0
6
LVIRSTD
TSTOP
MS0B
13
13
13
13
5
0
0
0
0
0
1
0
5
0
1
5
1
0
5
0
0
5
R = Reserved
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
LVIPWRD
MS0A
MS1A
TRST
12
12
12
12
4
0
0
0
0
0
0
0
0
4
0
1
4
1
0
4
0
4
LVI5OR3
ELS0B
ELS1B
IRQF
11
11
11
11
3
0
0
0
0
0
0
0
3
0
1
3
1
0
3
0
3
SSREC
ELS0A
ELS1A
ACK
PS2
10
10
10
10
Input/Output (I/O) Section
U = Unaffected
2
0
0
0
0
0
0
0
2
0
1
2
1
0
2
0
2
STOPENB
IMASK
STOP
TOV0
TOV1
OSC-
PS1
1
0
0
0
0
9
0
1
0
9
1
1
1
0
9
1
0
9
1
SCIBDSRC
CH0MAX
CH1MAX
MODE
COPD
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PS0
0
0
0
0
0
0
1
1
0
0
33

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