M30280F6HP#D7 Renesas Electronics America, M30280F6HP#D7 Datasheet - Page 202

• Manufacturer Part Number: M30280F6HP#D7
• Description: MCU 3/5V 48K I-TEMP 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
e
E
1
Figure 14.11 Polarity of transfer clock
Figure 14.12 Transfer format
. v
J
6
0
C
2
9
2 /
0 .
B
14.1.1.3 LSB First/MSB First Select Function
0
8
0
0
Use the UFORM bit in the UiC0 register (i=0 to 2) to select the transfer format. Figure 14.12 shows the
transfer format.
G
4
14.1.1.2 CLK Polarity Select Function
J
7
a
o r
Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11
shows the polarity of the transfer clock.
0 -
. n
u
2
3
p
0
, 1
0
(
NOTES:
i = 0 to 2
(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling
R
(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising
R
CLK
T
CLK
T
M
(1) When the UFORM bit in the UiC0 register "0" (LSB first)
(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)
2
X
X
X
X
CLK
T
R
CLK
T
R
NOTES:
i = 0 to 2
D
D
0
D
D
1
1. This applies to the case where the UFORM bit in the UiC0 register is set to "0" (LSB
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
X
X
edge and the receive data taken in at the rising edge of the transfer clock)
X
X
edge and the receive data taken in at the falling edge of the transfer clock)
i
i
0
i
i
i
i
6
D
D
D
D
1. This applies to the case where the CKPOL bit in the UiC0 register is
7
C
i
i
i
i
i
i
first) and the UiLCH bit in the UiC1 register is set to "0" (no reverse).
2 /
set to "0" (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock) and the UiLCH
bit in the UiC1 register "0" (no reverse).
page 180
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M
1
6
C
D0
D
D
D
0
0
0
2 /
f o
D0
D
D
D
8
3
0
7
7
) B
8
D
D
D
D
5
1
1
1
1
D
D
D
D
1
6
1
6
D
D
D
D
2
2
2
2
D
D
D
D
D
D
D
D
2
5
2
5
3
3
3
3
D
D
D
D
D
D
D
D
3
3
4
4
4
4
4
4
D
D
D
D
D
D
D
D
5
5
5
5
4
3
4
3
D
D
D
D
6
6
6
6
D
D
D
D
5
5
2
2
D
D
D
D
7
7
7
7
D
D
D
D
6
6
1
1
D
D
D
D
7
7
0
0
(2)
(3)
14.Serial I/O