M30280F6HP#D7 Renesas Electronics America, M30280F6HP#D7 Datasheet - Page 422

• Manufacturer Part Number: M30280F6HP#D7
• Description: MCU 3/5V 48K I-TEMP 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.
REVISION HISTORY
Date
Page
163
166
175
183
191
193
201
207
212
216
217
220
222
251
253
274
275
282
284
294
296
297
302
306
307
308
310
• Table 13.11 Pin Setting for Time Measurement and Waveform Generating
Serial I/O
• Figure 14.1 Block Diagram of UARTi Partially modified
• Table 14.1 Clock Synchronous Serial I/O Mode Specifications Note 2 modi-
• Table 14.5 UART Mode Specifications Note 1 modified
• Table 14.10 I
• Table 14.11 Registers to Be Used and Settings in I
• Table 14.15 Special Mode 2 Specifications Note 2 modified
• Table 14.18 SIM Mode Specifications Note 1 modified
• 14.2 SI/O3 and SI/O4 Note is added
• 14.2.3 Functions for Setting an SOUTi Initial Value modified
A/D Converter
• Table 15.1 A/D Converter Performance Note 2 partially added
• Table 15.2 A/D Conversion Frequency Select note 1 modified
• Figure 15.5 TB2SC Register Note 4 partially modified
Multi-Master I
• Figure 16.1 Block Diagram of Multi-master I
• Figure 16.3 S00 Register Register name in Note 1 modified
• 16.11 STOP Condition Generation Method Description partially added
• Table 16.8 Start/Stop Generation Timing Table Number of cycle partially
Programmable I/O Ports
• 17.3 Pull-up Control Register 0 to 2 Description modified
• Figure 17.1 I/O Ports (1) A port P8
• Figure 17.12 Digital Debounce Filter P8
Flash Memory
• Table 18.1 Flash Memory Version Specifications Specification modified
• 18.1.1 Boot Mode Newly added
• 18.3.1 ROM Code Potect Function Description is modified
• 18.5.1 Flash Memory Control Register 0 (FMR0) Descriptions in FMR01 Bit
• 18.5.2 Flash Memory Control Register 1 (FMR1) Description in FMR16 Bit
• Figure 18.7 FMR1 Register Note 3 modified
• Figure 18.10 Setting and Resetting of EW Mode 1 note mark (3) added
Functions Description of port direction modified
fied
partially deleted
deleted, input from system clock select circuit modified
modified
and FMR02 Bit modified
and FMR17 Bit modified
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
2
2
C bus Interface
C bus Mode Specifications Note 2 modified
C-15
Description
Summary
1
added
5
, NMI, SD, and INPC17 are deleted
_______ _____
2
C bus Interface S30 register
2
C bus Mode Note mark