M30280F6HP#D7 Renesas Electronics America, M30280F6HP#D7 Datasheet - Page 65

• Manufacturer Part Number: M30280F6HP#D7
• Description: MCU 3/5V 48K I-TEMP 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D7

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
Figure 6.3 Bus Block Diagram
Table 6.1 Accessible Area and Bus Cycle
J
6
0
The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to
interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-
eral bus. Figure 6.3 shows the block diagram of the internal bus.
The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.
SFR
ROM/RAM
C
2
9
0 .
2 /
B
0
0
8
0
4
G
J
7
a
o r
0 -
. n
Clock
generation
circuit
DMAC
u
2
3
CPU
p
0
, 1
0
(
M
CPU clock
2
PM20 bit = 0 (2 waits)
PM20 bit = 1 (1 wait)
PM17 bit = 0 (no wait)
PM17 bit = 1 (1 wait)
0
1
0
6
7
C
2 /
CPU address bus
CPU data bus
Accessible Area
, 8
Peripheral function
page 43
M
1
6
C
f o
2 /
8
3
) B
8
5
BIU
3 CPU clock cycles
2 CPU clock cycles
1 CPU clock cycle
2 CPU clock cycles
Bus Cycle
ROM
Memory address bus
Memory data bus
Serial I/O
Timer
WDT
ADC
I/O
.
.
.
.
RAM
6. Processor Mode