SAF-C167CS-L33M CA+ Infineon Technologies, SAF-C167CS-L33M CA+ Datasheet - Page 18
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SAF-C167CS-L33M CA+
Manufacturer Part Number
SAF-C167CS-L33M CA+
Description
IC MCU 16BIT ROM/LESS MQFP-144
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAK-C167CS-LM_CA.pdf
(81 pages)
Specifications of SAF-C167CS-L33M CA+
Core Processor
C166
Core Size
16-Bit
Speed
33MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Type
ROMless
Ram Size
11K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144- BSQFP
Data Bus Width
16 bit
Data Ram Size
11 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
111
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Packages
PG-MQFP-144
Max Clock Frequency
33.0 MHz
Sram (incl. Cache)
11.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
24
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
SAFC167CSL33MCAT
SP000016731
SP000016732
SP000016731
SP000016732
Functional Description
The architecture of the C167CS combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
Figure 3
high bandwidth internal bus structure of the C167CS.
Note: All time specifications refer to a CPU clock of 40 MHz
Figure 3
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see
The XBUS resources (XRAM, CAN) of the C167CS can be individually enabled or
disabled during initialization. Register XPERCON selects the required modules which
are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2).
Modules that are disabled consume neither address space nor port pins.
Note: The default value of register XPERCON after reset selects 2 KByte XRAM and
Data Sheet
8
8
(see definition in the AC Characteristics section).
module CAN1, so the default XBUS resources are compatible with the C167CR.
gives an overview of the different on-chip components and of the advanced,
Rev 2.0B active
Rev 2.0B active
ProgMem
32 KByte
6+2 KByte
XRAM
CAN2
CAN1
ROM
Port 0
XBUS Control
Block Diagram
External Bus
16
Control
EBC
Instr. / Data
Port 1
16
16
16
32
Channels
ADC
10-Bit
16+8
Port 5
External Instr. / Data
16
(USART)
ASC0
BRGen
Interrupt Controller 16-Level
C166-Core
CPU
BRGen
SSC
(SPI)
14
Port 3
15
PEC
Priority
GPT
T2
T3
T4
T5
T6
Interrupt Bus
PWM
Peripheral Data Bus
Port 7
Data
Data
8
16
CCOM2
16
16
T7
T8
RTC
CCOM1
Osc / PLL
Port 8
8
T0
T1
3 KByte
IRAM
Internal
MCB04323_7CS
RAM
C167CS-4R
WDT
Figure
V2.2, 2001-08
C167CS-L
16
XTAL
3).