SAF-XC167CI-16F40F BB Infineon Technologies, SAF-XC167CI-16F40F BB Datasheet - Page 49
![IC MCU 16BIT 128KB TQFP-144-19](/photos/39/69/396957/qfp144_sml.jpg)
SAF-XC167CI-16F40F BB
Manufacturer Part Number
SAF-XC167CI-16F40F BB
Description
IC MCU 16BIT 128KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC167CI-16F20F_BB.pdf
(90 pages)
Specifications of SAF-XC167CI-16F40F BB
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
103
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
2xASC, 2xSSC, 1xI2C
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
103
Number Of Timers
11
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Packages
PG-TQFP-144
Max Clock Frequency
40.0 MHz
Sram (incl. Cache)
8.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
16
Program Memory
128.0 KByte
For Use With
B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FX167CI16F40FBBNP
FX167CI16F40FBBXP
SAFXC167CI16F40FBBT
SP000094529
SP000224690
FX167CI16F40FBBXP
SAFXC167CI16F40FBBT
SP000094529
SP000224690
3.13
The integrated TwinCAN module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module’s resources to optimize the CAN bus
traffic handling and to minimize the CPU load. The module provides up to 32 message
objects, which can be assigned to one of the CAN nodes and can be combined to FIFO-
structures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces the
efforts to fulfill the real-time requirements of complex embedded control applications.
Improved CAN bus monitoring functionality as well as the number of message objects
permit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bus
systems, which reduces CPU load and improves the real time behavior of the entire
system.
The bit timing for both CAN nodes is derived from the master clock and is programmable
up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 4, Port 7, or Port 9 to
interface to an external bus transceiver. The interface pins are assigned via software.
Figure 10
Data Sheet
Decoder
Address
Interrupt
Control
Control
Clock
TwinCAN Module
TwinCAN Module Block Diagram
f
CAN
TwinCAN Module Kernel
Node A
TwinCAN Control
CAN
Message
Object
Buffer
Node B
CAN
47
RxDCA
RxDCB
TxDCA
TxDCB
Functional Description
Control
Port
XC167CI-16F
Derivatives
V1.3, 2006-08
MCB05567