MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 637

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

25.6
The FlexCAN module is flexible in that each one of its 32 message buffers (MBs) can be assigned either
as a transmit buffer or a receive buffer. Each MB, which is up to 8 bytes long, is also assigned an interrupt
flag bit that indicates successful completion of either transmission or reception.
An arbitration algorithm decides the prioritization of MBs to be transmitted based on either the message
ID or the MB ordering. A matching algorithm makes it possible to store received frames only into MBs
that have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID
programmed on the MB with a range of IDs on received CAN frames. Data coherency mechanisms are
implemented to guarantee data integrity during MB manipulation by the CPU.
Before proceeding with the functional description, an important concept must be explained. A message
buffer is said to be active at a given time if it can participate in the matching and arbitration algorithms that
are happening at that time. An Rx MB with a 0000 code is inactive (refer to
MB with a 1000 code is inactive (refer to
will be temporarily deactivated (will not participate in the current arbitration/matching run) when the CPU
writes to the C/S field of that MB.
25.6.1
The CPU prepares or changes an MB for transmission by writing the following:
Freescale Semiconductor
MBn[RTR]
1. Control/status word to hold Tx MB inactive (CODE = 1000)
2. ID word
3. Data bytes
4. Control/status word (active CODE, LENGTH)
0
0
Functional Overview
Tx Code
Transmit Process
Initial
1010
1110
The first and last steps are mandatory.
Transmission
Successful
Code After
Table 25-13. Message Buffer Code for Tx Buffers (continued)
1010
1010
Transmit a data frame whenever a remote request frame with the same ID is received.
This message buffer participates simultaneously in both the matching and arbitration
processes. The matching process compares the ID of the incoming remote request
frame with the ID of the MB. If a match occurs, this message buffer is allowed to
participate in the current arbitration process and the CODE field is automatically
updated to 1110 to allow the MB to participate in future arbitration runs. When the frame
is eventually transmitted successfully, the code automatically returns to 1010 to restart
the process again.
This is an intermediate code that is automatically written to the message buffer as a
result of match to a remote request frame. The data frame will be transmitted
unconditionally once, and then the code will automatically return to 1010. The CPU can
also write this code with the same effect.
MCF5253 Reference Manual, Rev. 1
Table
25-13). An MB not programmed with either 0000 or 1000
NOTE
Description
Table
25-12). Similarly, a Tx
FlexCAN Module
25-21