MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 91

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

5.4.2
For every memory reference the ColdFire core or the debug module generates, a set of “effective
attributes” is determined based on the address and the Access Control Registers (ACR0, ACR1). This set
of attributes includes the cacheable/noncacheable definition, the precise/imprecise handling of operand
write, and the write-protect capability.
In particular, each address is compared to the values programmed in the Access Control Registers (ACR).
If the address matches one of the ACR values, the access attributes from that ACR are applied to the
reference. If the address does not match either ACR, then the default value defined in the Cache Control
Register (CACR) is used. The specific algorithm is as follows:
5.4.3
The instruction cache does not monitor ColdFire core data references for accesses to cached instructions.
Therefore, software must maintain cache coherency by invalidating the appropriate cache entries after
modifying code segments.
The cache invalidation can be performed in two ways. The assertion of bit 24 in the CACR forces the entire
instruction cache to be marked as invalid. The invalidation operation requires 512 cycles because the cache
sequences through the entire tag array, clearing a single location each cycle. Any subsequent instruction
fetch accesses are postponed until the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed,
the cache entry defined by bits[12:4] of the source address register is invalidated, provided bit 28 of the
CACR is cleared.
These invalidation operations can be initiated from the ColdFire core or the debug module.
5.4.4
A hardware reset clears the CACR disabling the instruction cache. The contents of the tag array are not
affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by
setting CACR[24] before the cache can be enabled.
5.4.5
As detailed in
line fill buffer for providing temporary storage for the last fetched instruction.
With the cache enabled as defined by CACR[31], a cacheable instruction fetch that misses in both the tag
memory and the line-fill buffer generates a external fetch. The size of the external fetch is determined by
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if (address = ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address = ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
Memory Reference Attributes
Cache Coherency and Invalidation
Reset
Cache Miss Fetch Algorithm/Line Fills
Section 5.1, “Instruction Cache Features,”
MCF5253 Reference Manual, Rev. 1
the instruction cache hardware includes a 16-byte
Instruction Cache
5-3