MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 240
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139412/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Ethernet Module
11.5.12 FIFO Transmit Start Register (TFSR)
The TFSR register,
transmit FIFO. Usually there is no need to program TFSR. For optimal RAM allocation, do not program
TFSR to a value less than its reset value. The value in this register must be added to MBAR + 0x800 to
determine the absolute address.
The TFSR register is reset to the first available RAM address.
Table 11-19
11-22
31–11
Bits
9–2
1–0
10
Reset
Reset
Field
Field
Addr
R/W
R/W
X_FSTART
describes the TFSR fields.
31
15
Name
—
—
—
Figure
0000_0
MCF5272 ColdFire
Reserved, should be cleared.
Reserved, should be set.
Transmit FIFO starting address. Address of first transmit FIFO location.
Reserved, should be cleared.
—
11-16, can be programmed by the user to indicate the starting address of the
Figure 11-16. FIFO Transmit Start Register (TFSR)
Table 11-19. TFSR Field Descriptions
11
®
Integrated Microprocessor User’s Manual, Rev. 3
10
1
1
0000_0000_0000_0000
9
MBAR + 0x8EC
Read/Write
Read/Write
—
Description
X_FSTART
0001_1000
Freescale Semiconductor
2
1
00
—
16
0
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