MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 434
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139412/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
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Signal Descriptions
After a device reset, INT[4:1] are enabled but the function is masked. INT4/DIN3 function can be changed
by software. INT[3:1] functions are always assigned to dedicated pins.
Interrupts INT[6:4] are multiplexed with other functions as follows:
INT1 is also internally connected to the USC_WOR function.
The INT6 function is always available regardless of the other functions enabled on this pin.
19.9
Each of the three GPIO ports is 16 bits wide. Each port line can be individually configured as input or
output. Except where indicated, each pin function is independently selectable between the corresponding
port pin or the other functions that may be multiplexed onto the pin. After reset all pins multiplexed with
GPIO signals default to inputs.
Port A general purpose I/O, PA[15:8] are multiplexed with PLIC TDM port 1 pins.
Port A general purpose I/O, PA[6:0] are multiplexed with USB module signals. PA7 is multiplexed with
QSPI_CS3 and DOUT3.
Port B general purpose I/O, PB[4:0] are multiplexed with the UART0 interface pins. If the UART0
interface is enabled, PB[4:0] are unavailable. PB5 is multiplexed with TA. PB6 is dedicated. PB7 is
multiplexed with TOUT0.
Port B general purpose I/O, PB[15:8] are multiplexed with the Ethernet interface pins. If the Ethernet
interface is enabled, PB[15:8] are unavailable.
Port C general purpose I/O, PC[15:0] are multiplexed with D[15:0]. When 32-bit wide bus mode is
selected, port C is unavailable.
19.10 UART0 Module Signals and PB[4:0]
The UART0 module uses the signals in this section for data and clock signals.
These signals are multiplexed with the GPIO port B signals PB[4:0].
19.10.1 Transmit Serial Data Output (URT0_TxD/PB0)
UART0 mode: URT0_TxD is the transmitter serial data output for the UART0 module. The output is held
high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted
out, lsb first, on this pin at the falling edge of the serial clock source.
Port B mode: This pin can also be configured as the PB0 I/O.
19-24
•
•
•
DGNT1_INT6/PA15_INT6
INT5/URT1_RTS
INT4/DIN3
General-Purpose I/O (GPIO) Ports
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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