MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 74
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139412/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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ColdFire Core
from the reset exception vector, address 0x0000. The same register is used for user and supervisor modes,
and may be used for word and longword operations.
A subroutine call saves the program counter (PC) on the stack and the return restores the PC from the stack.
The PC and the status register (SR) are saved on the stack during exception and interrupt processing. The
return from exception instruction restores SR and PC values from the stack.
2.2.1.4
The PC holds the address of the executing instruction. For sequential instructions, the processor
automatically increments the PC. When program flow changes, the PC is updated with the target
instruction. For some instructions, the PC specifies the base address for PC-relative operand addressing
modes.
2.2.1.5
The CCR,
results generated by arithmetic operations.
CCR fields are described in
2-6
Bits
7–5
4
3
2
1
0
Name
Figure
—
X
N
V
C
Z
Program Counter (PC)
Condition Code Register (CCR)
Reserved, should be cleared.
Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not
affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic.
Negative condition code bit. Set if the msb of the result is set; otherwise cleared.
Zero condition code bit. Set if the result equals zero; otherwise cleared.
Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be
represented in the operand size; otherwise cleared.
Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition or if a borrow
occurs in a subtraction; otherwise cleared.
2-4, occupies SR[7–0], as shown in
MCF5272 ColdFire
Reset
Field
R/W
Table
Figure 2-4. Condition Code Register (CCR)
7
2-1.
Table 2-1. CCR Field Descriptions
000
—
R
®
6
Integrated Microprocessor User’s Manual, Rev. 3
5
R/W
X
4
Description
Figure
R/W
N
3
2-3. CCR[4–0] are indicator flags based on
Undefined
R/W
Z
2
R/W
V
1
R/W
C
0
Freescale Semiconductor
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