MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 373

• Manufacturer Part Number: MCF5272VF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Table 16-9
Freescale Semiconductor
Bits
7
6
5
4
3
2
1
0
Address
Reset
FFULL/R
Field
RxFIFO
TxFIFO
RxFTO
TxRDY
R/W
Name
xRDY
COS
ABC
DB
describes UISRn and UIMRn fields.
COS
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt.
Autobaud calculation.
0 Autobaud is disabled or is waiting for the first receiver character.
1 The baud rate has been calculated and loaded into the clock source divider (UDUn and UDLn).
After being set, this bit is cleared by writing to UCRn[ENAB].
Receiver FIFO status. After being set, this bit is cleared by reading URBn.
0 FIFO status indication is disabled or the receiver status has not changed.
1 The receiver status has changed as programmed in URFn[RXS].
Transmitter FIFO status. After being set, this bit is cleared by writing UTBn.
0 FIFO status indication is disabled or the transmitter status has not changed.
1 The transmitter status has changed as programmed in UTFn[TXS].
Receiver FIFO timeout.
0 No receiver FIFO timeout. This bit is cleared by reading all remaining data in the receiver FIFO, by
1 The receiver FIFO has timed out at 64 baud with unread data below the FIFO fullness level.
Delta break.
0 No new break-change condition to report.
1 The receiver detected the beginning or end of a received break.
RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY] = 1.
Duplicate of USRn[FFULL/RxRDY].
Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded
1 The transmitter holding register is empty and ready to be loaded with a character.
7
receiving another character into the FIFO, or if the receiver is disabled. The count to timeout is restarted
when RxFTO is cleared.
the
into the transmitter holding register when TxRDY = 0 are not sent.
Figure 16-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
RESET BREAK
MCF5272 ColdFire
MBAR + 0x114 (UISR0), 0x154 (UISR1); MBAR + 0x114 (UIMR0), 0x154 (UIMR1)
ABC
6
Table 16-9. UISRn/UIMRn Field Descriptions
-
CHANGE INTERRUPT
RXFIFO
®
Read only for status, write only for mask.
Integrated Microprocessor User’s Manual, Rev. 3
TXFIFO
command.
0000_0000
Section 16.3.5, “UART Command Registers
Description
RXFTO
3
DB
2
FFULL/RxRDY
1
(UCRn),” describes
TxRDY
UART Modules
0
16-13