MCF5272VF66 Freescale Semiconductor, MCF5272VF66 Datasheet - Page 333
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139412/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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13.6.2.2
The PnICR registers should be configured according to the specific interrupts, periodic and aperiodic,
required for each port. In addition, the port interrupt enable, (PnICR[IE]) should be set for each active port
prior to receiving interrupts.
Assuming port 1 is configured as in the above example then the following configuration would enable
periodic interrupts on port 1 with only the D channel active.
The programming of the P1ICR in the above example is achieved with the following ColdFire code
sequence assuming the equates and init sections as in the previous P1CR example:
...
move.w
move.w
...
Freescale Semiconductor
Port 0 only
IE enabled
GCI only
Interrupt Configuration Example
P1ICR
#0x8024,d0
d0,P1ICR(A5)
0x
MCF5272 ColdFire
Figure 13-36. Port 1 Interrupt Configuration Register (P1ICR)
15 14 13 12 11 10
1
0
8
0
0
®
; port 1 IE and D-channel interrupts enabled
; write value to PnICR
Integrated Microprocessor User’s Manual, Rev. 3
0
0
0
9
0
8
0
7
0
6
0
2
5
1
4
0
3
0
Physical Layer Interface Controller (PLIC)
2
1
4
1
0
0
0
Reserved
DTIE enabled
B2TIE disabled
B1TIE disabled
DRIE enabled
B2RIE disabled
B1RIE disabled
13-37
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