XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet
XR17C158CV-F
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XR17C158CV-F Summary of contents
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AUGUST 2005 GENERAL DESCRIPTION 1 The XR17C158 (158 octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement systems. The global interrupt provides a complete interrupt ...
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... VCC 138 AD31 139 AD30 140 AD29 AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION P N ART UMBER XR17C158CV 144-Lead LQFP XR17C158IV 144-Lead LQFP XR17C158 ACKAGE PERATING EMPERATURE 0°C to +70°C -40°C to +85° REV. 1.4.3 72 CTS5# 71 RX5 ENIR ...
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REV. 1.4.3 PIN DESCRIPTIONS Pin Description AME IN PCI LOCAL BUS INTERFACE RST# 134 CLK 135 AD31-AD25, 138-144, AD24, 1, AD23-AD16, 6-13, AD15-AD8, 26-33, AD7-AD0 37-44 FRAME# 15 C/BE0#-C/BE3# 36,25,14,2 IRDY# 16 TRDY# 17 STOP# ...
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XR17C158 5V PCI BUS OCTAL UART Pin Description AME IN DTR1# 118 DSR1# 122 CD1# 121 RI1# 120 TX2 106 RX2 99 RTS2# 104 CTS2# 100 DTR2# 105 DSR2# 101 CD2# 102 RI2# 103 TX3 98 ...
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REV. 1.4.3 Pin Description AME IN TX6 62 RX6 55 RTS6# 60 CTS6# 56 DTR6# 61 DSR6# 57 CD6# 58 RI6# 59 TX7 54 RX7 47 RTS7# 52 CTS7# 48 DTR7# 53 DSR7# 49 CD7# ...
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XR17C158 5V PCI BUS OCTAL UART Pin Description AME IN EECS 115 EEDI 114 EEDO 113 XTAL1 110 XTAL2 109 TMRCK 69 ENIR 70 TEST# 111 VCC 4,19,34,45,64, 90,112,137 GND 5,20,35,46,63, 89,136 N : Pin type: ...
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REV. 1.4.3 FUNCTIONAL DESCRIPTION The XR17C158 (158) integrates the functions of 8 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/counter, 8 multi-purpose inputs/outputs, and an ...
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XR17C158 5V PCI BUS OCTAL UART 1.0 XR17C158 REGISTERS The XR17C158 UART has three different sets of registers as shown in configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI bus. This auto-configuration feature makes ...
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REV. 1.4 PCI L ABLE DDRESS ITS YPE 0x00 31:16 Device ID (Exar device ID number) 1 RWR 15:0 Vendor ID (Exar) specified by PCISIG 1 RWR 0x04 31 RWC Parity error detected. Cleared ...
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XR17C158 5V PCI BUS OCTAL UART T 1: PCI L ABLE DDRESS ITS YPE 0x2C 31:16 1 Subsystem ID (write from external EEPROM by customer) RWR 15:0 1 Subsystem Vendor ID (write from external EEPROM by cus- ...
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REV. 1.4 XR17C158 D ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 - 0x0FF Reserved 0x100 - 0x13F ...
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XR17C158 5V PCI BUS OCTAL UART T 2: XR17C158 D ABLE FFSET DDRESS EMORY PACE 0x740 - 0x77F Reserved 0x780 - 0x7FF UART 3 – Read FIFO with errors 0x800 - 0x80F UART channel 4 Regs ...
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REV. 1.4 XR17C158 D ABLE FFSET DDRESS EMORY PACE 0xF40 - 0xF7F Reserved 0xF80 - 0xFFF UART 7 – Read FIFO with errors C R EVICE ONFIGURATION EGISTERS EAD ...
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XR17C158 5V PCI BUS OCTAL UART ABLE EVICE A [A7:A0] R DDRESS EGISTER Ox080 INT0 [7:0] Ox081 INT1 [15:8] Ox082 INT2 [23:16] Ox083 INT3 [31:24] Ox084 TIMERCNTL Ox085 TIMER Ox086 TIMERLSB Ox087 TIMERMSB Ox088 8XMODE Ox089 REGA ...
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REV. 1.4.3 1.2.1 The Interrupt Status Register The XR17C158 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme is an 8-bit indicator representing all 8 channels ...
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XR17C158 5V PCI BUS OCTAL UART . IGURE HE LOBAL NTERRUPT INT3 Register Channel-7 Channel-6 Channel-5 Bit Bit Bit Bit Bit Bit Bit Bit N+2 N+1 N N+2 N+1 N N+2 N UART ...
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REV. 1.4.3 1.2.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL XX-XX-00-00 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal crystal oscillator or externally on pin ...
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XR17C158 5V PCI BUS OCTAL UART TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is bit [0] of the TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these ...
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REV. 1.4.3 1.2.6 SLEEP [31:24] - (default 0x00) The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. All of these conditions ...
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XR17C158 5V PCI BUS OCTAL UART REGB [23:16] (default 0x00) REGB register provides a control for simultaneous write to all 8 UARTs configuration register or individually. This is very useful for device initialization during power-up and reset routines. Also, the ...
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REV. 1.4 IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) MPIOSEL [7:0] (Select Input=1, Output=0 ) MPIOINT ...
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XR17C158 5V PCI BUS OCTAL UART MPIOLVL [7:0] (default 0x00) Output pin level control and input level status. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 ...
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REV. 1.4.3 2.0 CRYSTAL OSCILLATOR / BUFFER The 158 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the 8 UARTs, the 16-bit general purpose ...
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XR17C158 5V PCI BUS OCTAL UART 3.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each ...
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REV. 1.4.3 Channel ReceiveData in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00 Receive Data Byte n ...
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XR17C158 5V PCI BUS OCTAL UART Channel Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00 Transmit Data Byte n ...
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REV. 1.4.3 4.0 UART There are 8 UARTs [channel 7:0] in the 158. Each has its own 64-byte of transmit and receive FIFOs, a set of 16550 compatible control and status registers, and a baud rate generator for individual ...
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XR17C158 5V PCI BUS OCTAL UART ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7=0 100 400 600 2400 1200 4800 2400 9600 4800 19.2k 9600 38.4k 19.2k ...
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REV. 1.4 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) 4.2.3 Transmitter Operation in FIFO mode The host may fill the transmit FIFO with up to ...
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XR17C158 5V PCI BUS OCTAL UART F 11 IGURE RANSMITTER PERATION IN Transmit Data Byte Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X or 8X Clock (8XMODE Register) Auto CTS Flow Control (CTS# pin) ...
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REV. 1.4.3 4.3.2 Receiver Operation in non-FIFO Mode F 12 IGURE ECEIVER PERATION IN NON 16X or 8X Clock (8XMODE Register) Error Receive Flags in Data Byte LSR bits and Errors 4:2 4.3.3 Receiver Operation in FIFO ...
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XR17C158 5V PCI BUS OCTAL UART 4.4 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output ...
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REV. 1.4.3 F 14. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts ...
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XR17C158 5V PCI BUS OCTAL UART 4.5 Infrared Mode Each UART in the 158 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 8 UART channels to ...
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REV. 1.4.3 4.6 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 16 shows ...
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XR17C158 5V PCI BUS OCTAL UART 4.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING The 8 sets of UART configuration registers are decoded using address lines A8 to A11 as shown below. Address lines select the 16 ...
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REV. 1.4 11: UART CHANNEL CONFIGURATION REGISTERS ABLE A DDRESS RHR - Receive Holding Register THR - Transmit Holding Register DLL ...
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XR17C158 5V PCI BUS OCTAL UART T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit ...
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REV. 1.4.3 T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE XCHAR XOFF1 W Bit-7 ...
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XR17C158 5V PCI BUS OCTAL UART IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in ...
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REV. 1.4.3 Interrupt Generation: • LSR is by any of the LSR bits and 4. • RXRDY trigger level. • RXRDY Time-out is by the a 4-char plus 12 bits delay timer if ...
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XR17C158 5V PCI BUS OCTAL UART ISR[4]: Xoff/Xon or Special Character Interrupt Status This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff character(s). ...
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REV. 1.4.3 FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receiv- er ...
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XR17C158 5V PCI BUS OCTAL UART 4.8.7 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are ...
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REV. 1.4.3 LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW ...
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XR17C158 5V PCI BUS OCTAL UART MCR[5]: Xon-Any Enable • Logic 0 = Disable Xon-Any function (for 16C550 compatibility) (default). • Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data transmission. ...
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REV. 1.4.3 LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In addition, this bit causes the UART ...
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XR17C158 5V PCI BUS OCTAL UART MSR[5]: DSR Input Status This input may be used for auto DTR/DSR flow control function, see (RTS/CTS or DTR/DSR) Flow Control Operation” on page 32 flow control is not used, this bit is the ...
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REV. 1.4.3 4.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a ...
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XR17C158 5V PCI BUS OCTAL UART T 17 ABLE ELECTABLE FCTR B -3 FCTR ...
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REV. 1.4.3 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR ...
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XR17C158 5V PCI BUS OCTAL UART EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/ DTR is selected, an interrupt will be ...
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REV. 1.4.3 REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-7:0] RTS#[ch-7:0] DTR#[ch-7:0] EECK EECS EEDI T 19: UART RESET CONDITIONS ...
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XR17C158 5V PCI BUS OCTAL UART 5.0 PROGRAMMING EXAMPLES These examples are for devices with top mark date codes of "GC YYWW" and older. 5 NLOADING ECEIVE ATA It is suggested that before starting to read ...
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REV. 1.4.3 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA (-40 ...
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XR17C158 5V PCI BUS OCTAL UART AC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA (-40 to +85 C for industrial grade package). VCC = 4.5 - 5.5V YMBOL ARAMETER XTAL1 UART Crystal ...
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REV. 1.4.3 F 17. PCI B C IGURE US ONFIGURATION CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# ...
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XR17C158 5V PCI BUS OCTAL UART F 18 IGURE EVICE ONFIGURATION AND CLK Host 1 2 FRAME# Host AD[31:0] Address Host Target Bus C/BE[3:0]# Byte Enable# = BYTE CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address PAR ...
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REV. 1.4 IGURE EVICE ONFIGURATION REGISTERS TION CLK Host FRAME# Host Data AD[31:0] Address DWORD Host Target Bus C/BE[3:0]# Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address ...
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XR17C158 5V PCI BUS OCTAL UART F 20 IGURE EVICE ONFIGURATION CLK Host 1 FRAME# Host AD[31:0] AD Host Target C/BE[3:0]# Bus Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# Target PAR AD Host Target ...
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REV. 1.4.3 F 21. 5V PCI B C (DC IGURE US LOCK 4 nSec (max) CLK Tvalid (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Bused Signal Input 33MH ) nSec 4 ...
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XR17C158 5V PCI BUS OCTAL UART F 22 IGURE RANSMIT ATA NTERRUPT AT START BIT TX Data TX Interrupt at Transmit Trigger Level F 23 IGURE ECEIVE ATA EADY START BIT RX Data Input ...
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REV. 1.4.3 PACKAGE DIMENSIONS 108 109 144 1 A Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL α 144 LEAD LOW-PROFILE QUAD ...
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XR17C158 5V PCI BUS OCTAL UART REVISION HISTORY D R ATE EVISION March 2000 Rev. 1.0.1 Preliminary March 2001 Rev. 1.0.2 Corrected patent number, front page; reference to DAN112; corrected CTS#, DSR#, RI# and CD# in figure 11 internal loopback; ...
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... REV. 1.4.3 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XRT99L00 PCI BUS OCTAL UART GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES ............................................................................................................................................................. 1 IGURE LOCK IAGRAM .................................................................................................................................................. 2 IGURE THE EVICE .................................................................................................................................2 ORDERING INFORMATION PIN ...
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REV. 1.4 IGURE ECEIVER PERATION IN NON 4.3.3 RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ........................................................................... IGURE ECEIVER PERATION IN 4.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION ...