XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 32
![IC UART PCI BUS 5V OCTAL 144LQFP](/photos/29/6/290690/lqfp144_sml.jpg)
XR17C158CV-F
Manufacturer Part Number
XR17C158CV-F
Description
IC UART PCI BUS 5V OCTAL 144LQFP
Manufacturer
Exar Corporation
Type
Universal PCI Bus Octal UARTr
Datasheet
1.XR17C158CV-F.pdf
(67 pages)
Specifications of XR17C158CV-F
Number Of Channels
8
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
6.25 Mbps
Supply Voltage (max)
7 V
Supply Current
5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
7 V
No. Of Channels
8
Uart Features
High Performance, Read/Write Burst Operation
Supply Voltage Range
-0.5V To 7V
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1287
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17C158CV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17C158CV-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR17C158
5V PCI BUS OCTAL UART
Automatic hardware RTS/CTS or DTR/DSR flow control is used to prevent data overrun to the local receiver
FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request the remote unit to suspend/
restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart the local transmitter.
The auto RTS/CTS or DTR/DSR flow control features are individually selected to fit specific application
requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control
signals.
Auto RTS flow control must be started by asserting the RTS# output pin LOW (MCR bit-1 = 1). Similarly, Auto
DTR flow control must be started by asserting the DTR# output pin LOW (MCR bit-0 = 1).
detail how automatic hardware flow control works.
Two interrupts associated with auto RTS/CTS and DTR/DSR flow control have been added to give indication
when RTS#/DTR# pin or CTS#/DSR# pin are de-asserted during operation. These interrupts are enabled by:
•
•
•
Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.
If CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit-5 will be set to logic 1, (if
enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns LOW, indicating more data may
be sent.
4.4
Setting EFR bit-4 =1 to enable the shaded register bits
Setting IER bit-7 will enable the CTS#/DSR# interrupt when these pins are de-asserted. The selection of
CTS# or DSR# is selected via MCR bit-2. See
Setting IER bit-6 will enable the RTS#/DTR# interrupt when these pins are de-asserted. The selection of
RTS# or DTR# is selected via MCR bit-2. See
MCR B
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
X
0
0
1
1
IT
-2
T
ABLE
10: A
EFR B
UTO
1
X
1
X
0
IT
-7
RTS/CTS
OR
Table 10
Table 10
DTR/DSR F
EFR B
32
X
X
1
1
0
IT
above for complete details.
above for complete details.
-6
LOW
C
ONTROL
Auto DSR Flow Control Enabled
Auto DTR Flow Control Enabled
Auto CTS Flow Control Enabled
Auto RTS Flow Control Enabled
F
LOW
S
ELECTION
No Flow Control
C
ONTROL
Figure 14
S
ELECTION
xr
REV. 1.4.3
shows in