XR17C158CV-F Exar Corporation, XR17C158CV-F Datasheet - Page 8

• Manufacturer Part Number: XR17C158CV-F
• Description: IC UART PCI BUS 5V OCTAL 144LQFP
• Manufacturer: Exar Corporation
• Type: Universal PCI Bus Octal UARTr

Specifications of XR17C158CV-F

• Number Of Channels: 8
• Package / Case: 144-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 7 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 7 V
• No. Of Channels: 8
• Uart Features: High Performance, Read/Write Burst Operation
• Supply Voltage Range: -0.5V To 7V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1287

XR17C158
5V PCI BUS OCTAL UART
The XR17C158 UART has three different sets of registers as shown in
configuration space registers are for plug-and-play auto-configuration when connecting the device to the PCI
bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI
local bus specification. The second register set is the device configuration registers that are accessible directly
from the PCI bus for programming general operating conditions of the device and monitoring the status of
various functions. These registers are mapped into 4K of the PCI bus memory address space. These functions
include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status,
multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision.
And lastly, each UART channel has its own set of internal UART configuration registers for its own operation
control and status reporting. All 8 sets of channel registers are embedded inside the device configuration
registers space, which provides faster access. The following paragraphs describe all 3 sets of registers in
detail.
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto
configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the
device vendor and sub-vendor data required by the auto-configuration setup.
F
1.0 XR17C158 REGISTERS
1.1
IGURE
D evic e
R eg is ter s ar e mapped on
byte
U AR T [7:0]
R eg is ter ( BAR ) in a 4K-
to the Bas e Addr es s
PC I Loc al Bus
3. T
PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
Inter fac e
of
C onfig ur ation
HE
memor y addr es s
s pac e
C onfig ur ation
XR17C158 R
and
EGISTER
S
ETS
C onfig ur ation
R eg is ter s for Plug -
and- Play
PC I Loc al Bus
C onfig ur ation
T IM ER , R EG
C hannel 2
C hannel 3
C hannel 4
C hannel 5
C hannel 6
C hannel 7
C hannel 0
C hannel 0
C hannel 1
IN T , M PIO ,
Auto
8
Spac e
0 x 0 0 0 0
0 x 0 0 8 0
0 x 0 2 0 0
0 x 0 4 0 0
0 x 0 6 0 0
0 x 0 8 0 0
0 x 0 A 0 0
0x0C 00
0x0E00
0x0F F F
Vendor
and Pr oduc t M odel N umber
in Exter nal EEPR O M
D evic e
16550 C ompatible and EXAR
Sleep, R es et, D VID , D R EV
and Sub- vendor
Figure
U AR T [7:0]
16- bit
8
Enhanc ed
M ultipur pos e
C onfig ur ation
c hannel
R eg is ter s
3. The PCI local bus
T imer /C ounter ,
C onfig ur ation
Inter r upts ,
R eg is ter s
xr
ID
I/O s ,
R eg is ter s
P CI RE G S -1
REV. 1.4.3