AD8362ARUZ Analog Devices Inc, AD8362ARUZ Datasheet - Page 16

• Manufacturer Part Number: AD8362ARUZ
• Description: IC PWR DETECTOR 3.8GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD8362ARUZ

• Rf Type: Cellular, GSM, CDMA, TDMA, TETRA
• Frequency: 50Hz ~ 3.8GHz
• Input Range: -52dBm ~ 8dBm
• Accuracy: 0.5dB
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Frequency Range: 50Hz To 3.8GHz
• Supply Current: 20mA
• Supply Voltage Range: 4.5V To 5.5V
• Rf Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Pin Count: 16
• Screening Level: Industrial
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8362
CIRCUIT DESCRIPTION
The AD8362 is a fully calibrated, high accuracy, rms-to-dc
converter providing a measurement range of over 65 dB. It is
capable of operating from signals as low in frequency as a few
hertz to at least 3.8 GHz. Unlike earlier rms-to-dc converters,
the response bandwidth is completely independent of the
signal magnitude. The −3 dB point occurs at about 3.5 GHz.
The capacity of this part to accurately measure waveforms
having a high peak-to-rms ratio (crest factor) is independent
of either the signal frequency or its absolute magnitude, over
a wide range of conditions.
This unique combination allows the AD8362 to be used as a
calibrated RF wattmeter covering a power ratio of >1,000,000:1,
a power controller in closed-loop systems, a general-purpose
rms-responding voltmeter, and in many other low frequency
applications.
The part comprises the core elements of a high performance
AGC loop (see Figure 44), laser-trimmed during manufacturing
to close tolerances while fully operational at a test frequency of
100 MHz. Its linear, wideband VGA provides a general voltage
gain, G
in-dB) manner over the full 68 dB range from −25 dB to +43 dB
by a voltage, V
only the central 60 dB of this range, from −21 dB to +39 dB, is
normally used. The Adjusting VTGT to Accommodate Signals
with Very High Crest Factors section shows how this basic
range can be shifted up or down.
CHPF
–25dB TO +43dB
VSET
VREF
INLO
INHI
SET
; this can be controlled in a precisely exponential (linear-
1.25V
NULLING
OFFSET
SET
SETPOINT
INTERFACE
REFERENCE
Figure 44. Basic Structure of the AD8362
VGA
BAND GAP
. However, to provide adequate guardbanding,
G
EXTERNAL
SET
V
SIG
BAND SQUARERS
I
MATCH WIDE-
CLPF
SQU
C
X
2
LPF
I
TGT
X
2
C
F
V
AMPLITUDE TARGET
INTERNAL
RESISTORS
SET BUFFER
GAIN TO 5
ATG
OUTPUT
FILTER
× 0.06
FOR V
SIG
VTGT
ACOM
VOUT
ACOM
Rev. D | Page 16 of 32
The VGA gain has the form
where:
G
V
change per volt). Note that the gain decreases with V
The VGA output is
where V
of the AD8362.
As explained in the Recommended Input Coupling section, the
input drive can either be single-sided or differential, although
dynamic range is maximized with a differential input drive. The
effect of high frequency imbalances when using a single-sided
drive is less apparent at low frequencies (from 50 Hz to 500 MHz),
but the peak input voltage capacity is always halved relative to
differential operation.
SQUARE LAW DETECTION
The output of the variable gain amplifier (V
a wideband square law detector, which provides a true rms
response to this alternating signal that is essentially independent
of waveform. Its output is a fluctuating current (I
a positive mean value. This current is integrated by an on-chip
capacitance (C
capacitance (CLPF) to extend the averaging time. The resulting
voltage is buffered by a gain of 5, dc-coupled amplifier whose
rail-to-rail output (VOUT) can be used for either measurement
or control purposes.
In most applications, the AGC loop is closed via the setpoint
interface pin, VSET, to which the VGA gain control voltage on
VOUT is applied. In measurement modes, the closure is direct
and local by a simple connection from the output of the VOUT
pin to the VSET pin. In controller modes, the feedback path is
around some larger system, but the operation is the same.
The fluctuating current (I
setpoint target current (I
With the exact integration provided by the capacitor(s), the
AGC loop equilibrates when
The current, I
cell whose input is the amplitude-target voltage V
a fraction of the voltage VTGT applied to a special interface,
which accepts this input at the VTGT pin. Because the two
squaring cells are electrically identical and are carefully imple-
mented in the IC, process and temperature-dependent variations
in the detailed behavior of the two square-law functions cancel.
Accordingly, VTGT (and its fractional part V
the output that must be provided by the VGA for the AGC
O
GNS
is a basic fixed gain.
G
V
MEAN(I
is a scaling voltage that defines the gain slope (the dB
SET
SIG
IN
= G
= G
is the ac voltage applied to the input terminals
SET
O
SQU
TGT
exp(−V
F
V
), which is usually augmented by an external
) = I
, is provided by a second-reference squaring
IN
= G
TGT
SET
O
V
/V
TGT
IN
SQU
GNS
exp(V
) using current mode subtraction.
) is balanced against a fixed
)
SET
/V
GNS
)
SIG
ATG
) is applied to
) determines
SQU
ATG
) that has
. This is
SET
.
(2)
(3)
(4)