AD8362ARUZ Analog Devices Inc, AD8362ARUZ Datasheet - Page 18

• Manufacturer Part Number: AD8362ARUZ
• Description: IC PWR DETECTOR 3.8GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD8362ARUZ

• Rf Type: Cellular, GSM, CDMA, TDMA, TETRA
• Frequency: 50Hz ~ 3.8GHz
• Input Range: -52dBm ~ 8dBm
• Accuracy: 0.5dB
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Frequency Range: 50Hz To 3.8GHz
• Supply Current: 20mA
• Supply Voltage Range: 4.5V To 5.5V
• Rf Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Pin Count: 16
• Screening Level: Industrial
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8362
An approximate schematic of the signal input section of the
AD8362 is shown in Figure 46. The ladder attenuator is com-
posed of 11 sections (12 taps), each of which progressively
attenuates the input signal by 6.33 dB. Each tap is connected to
a variable transconductance cell whose bias current determines
the signal weighting given to that tap. The interpolator determines
which stages are active by generating a discrete set of bias currents,
each having a Gaussian profile. These are arranged to move
from left to right, thereby determining the attenuation applied
to the input signal as the gain is progressively lowered over the
69.3 dB range under control of the VSET input. The detailed
manner in which the transconductance of adjacent stages varies
as the virtual tap point slides along the attenuator accounts for
the ripple observed in the conformance curves. Its magnitude is
slightly temperature dependent and also varies with frequency
(see Figure 10, Figure 11, and Figure 12). Notice that the system’s
responses to signal inputs at INHI and INLO are not completely
independent; these pins do not constitute a fully floating
differential input.
DECL
OFFSET ELIMINATION
To address the small dc offsets that arise in the VGA, an offset-
nulling loop is used. The high-pass corner frequency of this
loop is internally preset to 1 MHz, which is sufficiently low for
INLO
INHI
gm
GAUSSIAN INTERPOLATOR
STAGE 1
6.33dB
Figure 46. Simplified Input Circuit
gm
STAGE 2
6.33dB
gm
STAGE 11
6.33dB
gm
ATTENUATION
CONTROL
TO FIXED
GAIN STAGE
Rev. D | Page 18 of 32
most high frequency applications. When using the AD8362
in low frequency applications, the corner frequency can be
reduced as needed by the addition of a capacitor from the
CHPF pin to ground having a nominal value of 200 μF/Hz.
For example, to lower the high-pass corner frequency to
150 Hz, a capacitance of 1.33 μF is required. The offset
voltage varies depending on the actual gain at which the
VGA is operating, and thus on the input signal amplitude.
Baseline variations of this sort are a common aspect of all
VGAs, but they are more evident in the AD8362 because of the
method of its implementation, which causes the offsets to ripple
along the gain axis with a period of 6.33 dB. When an exces-
sively large value of CHPF is used, the offset correction process
can lag the more rapid changes in the VGA’s gain, which in turn
can increase the time required for the loop to fully settle for a
given steady input amplitude.
TIME-DOMAIN RESPONSE OF THE CLOSED LOOP
The external low-pass averaging capacitance (CLPF) added at
the output of the squaring cell is chosen to provide adequate
filtering of the fluctuating detected signal. The optimum value
depends on the application; as a guideline, a value of roughly
900 μF/Hz should be used. For example, a capacitance of 5 μF
provides adequate filtering down to 180 Hz. Note that the
fluctuation in the quasi-dc output of a squaring cell operating
on a sine wave input is a raised cosine at twice the signal
frequency, easing this filtering function.
In the standard connections for the measurement mode, the
VSET pin is tied to VOUT. For small changes in input ampli-
tude (a few decibels), the time-domain response of this loop
is essentially linear, with a 3 dB low-pass corner frequency of
nominally f
this local loop set the minimum recommended value of this
capacitor to about 300 pF, resulting in f
When large and abrupt changes of input amplitude occur,
the loop response becomes nonlinear and exhibits slew rate
limitations.
LP
= 1/(CLPF × 1.1 kΩ). Internal time delays around
LP
= 3 MHz.