AD8362ARUZ Analog Devices Inc, AD8362ARUZ Datasheet - Page 28

• Manufacturer Part Number: AD8362ARUZ
• Description: IC PWR DETECTOR 3.8GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD8362ARUZ

• Rf Type: Cellular, GSM, CDMA, TDMA, TETRA
• Frequency: 50Hz ~ 3.8GHz
• Input Range: -52dBm ~ 8dBm
• Accuracy: 0.5dB
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Frequency Range: 50Hz To 3.8GHz
• Supply Current: 20mA
• Supply Voltage Range: 4.5V To 5.5V
• Rf Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Pin Count: 16
• Screening Level: Industrial
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8362
AD8362 EVALUATION BOARD
The AD8362 evaluation board provides for a number of dif-
ferent operating modes and configurations, including many
described in this data sheet. The measurement mode is set up
by positioning SW2 as shown in Figure 67. The AD8362 can be
operated in controller mode by applying the setpoint voltage to
the VSET connector, and flipping SW2 to its alternate position.
The internal voltage reference is used for the target voltage when
SW1 is in the position shown in Figure 67. This voltage may
optionally be reduced via a voltage divider implemented with
R4 and R5, with LK1 in place, and SW1 switched to its alternate
position. Alternatively, an external target voltage may be used
PWDN
RFIN
1000pF
C10
T1
R13
10kΩ
SW3
AGND
1000pF
OPEN
R14
C8
100pF
100pF
C6
C5
OPEN
R15
R16
1000pF
0Ω
1000pF
C4
C7
Figure 67. Evaluation Board Schematic
VPOS
1
2
3
4
5
6
7
8
Rev. D | Page 28 of 32
COMM
CHPF
DECL
INHI
INLO
DECL
PWDN
COMM
0.1µF
C1
AD8362
ACOM
ACOM
VPOS
VOUT
R1
0Ω
VREF
VTGT
VSET
CLPF
with SW1 switched to its alternate position, LK1 removed, and
the external target voltage applied to the VTGT connector.
In measurement mode, the slope of the response at VOUT may
be increased by using a voltage divider implemented with resis-
tors in Position R17 and Position R9, and with SW2 switched to
its alternate position.
The AD8362 is powered up with SW3 in the position shown in
Figure 67 and connector PWDN open. The part can be powered
down by either connecting a logic high voltage to a connector,
PWDN, with SW3 in the position, or by switching SW3 to its
alternate position.
16
15
14
13
12
11
10
9
C2
100pF
R17
OPEN
R10
0Ω
R9
10kΩ
R6
0Ω
R8
0Ω
OPEN
0.1µF
C3
C9
SW1
0Ω
R4
SW2
R5
10kΩ
R7
0Ω
LK1
VREF
VOUT
VTGT
VSET