EM35X-DEV-IAR Ember, EM35X-DEV-IAR Datasheet - Page 102

• Manufacturer Part Number: EM35X-DEV-IAR
• Description: KIT DEV EM35X IAR EWARM ZIGBEE
• Manufacturer: Ember
• Series: EM35xr
• Type: Zigbeer

Specifications of EM35X-DEV-IAR

• Frequency: 2.4GHz
• For Use With/related Products: EM351, EM357
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1027

8.6.3
Characters transmitted and received by the UART are buffered in the transmit and receive FIFOs that are both
4 entries deep (see Figure 8-4). When software writes a character to the SC1_DATA register, it is pushed onto
the transmit FIFO. Similarly, when software reads from the SC1_DATA register, the character returned is
pulled from the receive FIFO. If the transmit and receive DMA channels are used, the DMA channels also write
to and read from the transmit and receive FIFOs.
8.6.4
RTS/CTS flow control, also called hardware flow control, uses two signals (nRTS and nCTS) in addition to
received and transmitted data (see Figure 8-5). Flow control is used by a data receiver to prevent buffer
overflow, by signaling an external device when it is and is not allowed to transmit.
The UART RTS/CTS flow control options are selected by the SC_UARTFLOW and SC_UARTAUTO bits in the
SC1_UARTCFG register (see Table 8-12). Whenever the SC_UARTFLOW bit is set, the UART will not start
transmitting a character unless nCTS is low (asserted). If nCTS transitions to the high state (deasserts) while a
character is being transmitted, transmission of that character continues until it is complete.
TXD
RXD
or
FIFOs
RTS/CTS Flow control
Idle time
Start
Bit
Data
Bit 0
Figure 8-5. RTS/CTS Flow Control Connections
Figure 8-3. UART Character Frame Format
Data
Bit 1
Data
Bit 2
Final
8-27
Figure 8-4. UART FIFOs
UART Character Frame Format
(optional sections are in italics)
Data
Bit 3
Data
Bit 4
Data
Bit 5
Data
Bit 6
Data
Bit 7
Parity
EM351 / EM357
Bit
Stop
Bit
Stop
Bit
120-035X-000G
IdleTime
Start Bit
Next
or