EM35X-DEV-IAR Ember, EM35X-DEV-IAR Datasheet - Page 151

KIT DEV EM35X IAR EWARM ZIGBEE

EM35X-DEV-IAR

Manufacturer Part Number
EM35X-DEV-IAR
Description
KIT DEV EM35X IAR EWARM ZIGBEE
Manufacturer
Ember
Series
EM35xr
Type
Zigbeer

Specifications of EM35X-DEV-IAR

Frequency
2.4GHz
For Use With/related Products
EM351, EM357
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1027
9.3.14.3
In this example (see Figure 9-34), the enable of Timer 2 is set with the UEV of Timer 1. Timer 2 starts counting
from its current value (which can be non-zero) on the divided internal clock as soon as Timer 1 generates the
UEV.
When Timer 2 receives the trigger signal its TIM_CEN bit is automatically set and the counter counts until 0 is
written to the TIM_CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (f
As in the previous example, both counters can be initialized before starting counting. Figure 9-35 shows the
behavior with the same configuration shown in Figure 9-34, but in trigger mode instead of gated mode
(TIM_SMS = 110 in the TIM2_SMCR register).
Configure Timer 1 in master mode to send its UEV as trigger output: WriteTIM_MMS = 010 in the TIM1_CR2
register.
Configure the Timer 1 period (TIM1_ARR register).
Configure Timer 2 to get the input trigger from Timer 1: Write TIM_TS = 000 in the TIM2_SMCR register.
Configure Timer 2 in trigger mode. Write TIM_SMS = 110 in the TIM2_SMCR register.
Start Timer 1: Write 1 in the TIM_CEN bit in theTIM1_CR1 register.
Using One Timer to Start the Other Timer
Figure 9-34. Triggering Timer 2 with Update of Timer 1
Figure 9-33. Gating Timer 2 with Enable of Timer 1
CK_CNT
= f
CK_INT
Final
9-27
/3).
120-035X-000G

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