EM35X-DEV-IAR Ember, EM35X-DEV-IAR Datasheet - Page 109

• Manufacturer Part Number: EM35X-DEV-IAR
• Description: KIT DEV EM35X IAR EWARM ZIGBEE
• Manufacturer: Ember
• Series: EM35xr
• Type: Zigbeer

Specifications of EM35X-DEV-IAR

• Frequency: 2.4GHz
• For Use With/related Products: EM351, EM357
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1027

SCx_DMACTRL
SC1_DMACTRL
Serial DMA Control Register
SC2_DMACTRL
Serial DMA Control Register
Bitname
SC_TXDMARST
SC_RXDMARST
SC_TXLODB
SC_TXLODA
SC_RXLODB
SC_RXLODA
31
23
15
0
0
0
7
0
8.7.1
30
22
14
6
0
0
0
0
Bitfield
[5]
[4]
[3]
[2]
[1]
[0]
Registers
SC_TXDMARST
29
21
13
5
0
0
0
Access
RW
RW
RW
RW
W
W
Setting this bit resets the receive DMA. The bit clears automatically.
start processing transmit buffer B. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this
bit has no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
Setting this bit loads DMA transmit buffer A addresses and allows the DMA controller to
start processing transmit buffer A. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this
bit has no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
Setting this bit loads DMA receive buffer B addresses and allows the DMA controller to
start processing receive buffer B. If both buffer A and B are loaded simultaneously, buffer
A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
Setting this bit loads DMA receive buffer A addresses and allows the DMA controller to
Description
Setting this bit resets the transmit DMA. The bit clears automatically.
Setting this bit loads DMA transmit buffer B addresses and allows the DMA controller to
start processing receive buffer A. If both buffer A and B are loaded simultaneously, buffer
A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
SC_RXDMARST
28
20
12
4
0
0
0
Final
8-34
SC_TXLODB
27
19
11
3
0
0
0
SC_TXLODA
26
18
10
0
0
0
2
Address: 0x4000C830 Reset: 0x0
Address: 0x4000C030 Reset: 0x0
EM351 / EM357
SC_RXLODB
25
17
0
0
9
0
1
120-035X-000G
SC_RXLODA
24
16
0
0
8
0
0