SI4133GX2M-EVB Silicon Laboratories Inc, SI4133GX2M-EVB Datasheet - Page 19

• Manufacturer Part Number: SI4133GX2M-EVB
• Description: BOARD EVAL DUAL-BAND GSM-HITACHI
• Manufacturer: Silicon Laboratories Inc
• Type: Synthesizerr

Specifications of SI4133GX2M-EVB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SI4133GX2M
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.7. RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO respectively. The
RF output amplifier receives its input from the RF1 or
RF2 VCO, depending on which R- or N-Divider register
is written last. For example, programming the N-Divider
register for RF1 automatically selects the RF1 VCO
output.
Figures 13 and 14 show application diagrams for the
Si4133. The RF output signal must be ac coupled to its
load through a capacitor. An external inductance
between the RFOUT pin and the ac coupling capacitor
is required as part of an output matching network to
maximize power delivered to the load. This 2 nH
inductance can be realized with a PC board trace. The
network is made to provide an adequate match to an
external 50  load for both the RF1 and RF2 frequency
bands. The matching network also filters the output
signal to reduce harmonic distortion.
The IFOUT pin must also be ac coupled to its load
through a capacitor. The IF output level is dependent
upon the load. Figure 18 on page 20 displays the output
level versus load resistance for a variety of output
frequencies. For resistive loads greater than 500  the
output level saturates and the bias currents in the IF
output amplifier are higher than required. The LPWR bit
in the Main Configuration register (Register 0) can be
set to 1 to reduce the bias currents and therefore reduce
the power dissipated by the IF amplifier. For loads less
than 500  LPWR should be set to 0 to maximize the
output level.
For IF frequencies greater than 500 MHz, a matching
network is required to drive a 50  load. See Figure 16.
The value of L
IFOUT
Frequency
500–600 MHz
600–800 MHz
800 MHz–1 GHz
Figure 16. IF Frequencies > 500 MHz
Table 10. L
MATCH
L
MATCH
can be determined from Table 10.
MATCH
560 pF
Values
L
40 nH
27 nH
18 nH
MATCH
50

Rev. 1.61
For frequencies less than 500 MHz, the IF output buffer
can directly drive a 200  resistive load or higher. For
resistive loads greater than 500  (f < 500 MHz) the
LPWR bit can be set to reduce the power consumed by
the IF output buffer. See Figure 17.
3.8. Reference Frequency Amplifier
The Si4133 provides a reference frequency amplifier. If
the driving signal has CMOS levels it can be connected
directly to the XIN pin. Otherwise, the reference
frequency signal should be ac coupled to the XIN pin
through a 560 pF capacitor.
3.9. Powerdown Modes
Table 11 summarizes the powerdown functionality. The
Si4133 can be powered down by taking the PWDN pin low
or by setting bits in the Powerdown register (Register 2).
When the PWDN pin is low, the Si4133 is powered down
regardless of the Powerdown register settings. When the
PWDN pin is high, power management is in control of the
Powerdown register bits.
The IF and RF sections of the Si4133 circuitry can be
individually powered down by setting the Powerdown
register bits PDIB and PDRB low, respectively. The
reference frequency amplifier is also powered up if the
PDRB and PDIB bits are high. Also, setting the AUTOPDB
bit to 1 in the Main Configuration register (Register 0) is
equivalent to setting both bits in the Powerdown register to
1.
The serial interface remains available and can be written in
all powerdown modes.
Figure 17. IF Frequencies < 500 MHz
IFOUT
>500 pF
>200
Si4133

19