ADF7021-NBCPZ Analog Devices Inc, ADF7021-NBCPZ Datasheet - Page 34
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ADF7021-NBCPZ
Manufacturer Part Number
ADF7021-NBCPZ
Description
IC TXRX 80-650/842-916MHZ 48LFCS
Manufacturer
Analog Devices Inc
Datasheet
1.ADF7021-NBCPZ-RL.pdf
(64 pages)
Specifications of ADF7021-NBCPZ
Frequency
80MHz ~ 650MHz, 842MHz ~ 916MHz
Data Rate - Maximum
33kbps
Modulation Or Protocol
2-FSK, 3-FSK, 4-FSK, MSK
Applications
Keyless Entery, Pagers, WMTS
Power - Output
-16dBm ~ 13dBm
Sensitivity
-130dBm
Voltage - Supply
2.3 V ~ 6 V
Current - Receiving
26mA
Current - Transmitting
32.3mA @ 10dBm
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LFCSP
Receiving Current
26.4mA
Transmitting Current
20.2mA
Data Rate
24Kbps
Frequency Range
80MHz To 916MHz
Modulation Type
FSK, MSK
Rf Ic Case Style
LFCSP
No. Of Pins
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
7mm
Product Length (mm)
7mm
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADF7021DBZ6 - BOARD EVAL ADF7021 608-614MHZEVAL-ADF7021DBZ5 - BOARD EVAL ADF7021EVAL-ADF7021DBZ3 - BOARD DAUGHTER FOR ADF7021EVAL-ADF7021DBZ2 - BOARD EVAL FOR ISM ADF7021
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF7021-NBCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADF7021-NBCPZ-RL7
Manufacturer:
ST
Quantity:
210
ADF7021-N
For example, using 2FSK with Manchester-encoded data
achieves a data rate tolerance of ±2.0%.
The CDR PLL is designed for fast acquisition of the recovered
symbols during preamble and typically achieves bit synchro-
nization within 5-symbol transitions of preamble.
In 4FSK modulation, the tolerance using the +3, −3, +3, −3
preamble is ±3% of the symbol rate (or ±1.5% of the data rate).
However, this tolerance is reduced during recovery of the
remainder of the packet where symbol transitions may not be
guaranteed to occur at regular intervals. To maximize the
symbol/data rate tolerance, the remainder of the 4FSK packet
should be constructed so that the transmitted symbols retain close
to dc-free properties by using data scrambling and/or by inserting
specific dc balancing symbols that are inserted in the transmitted
bit stream at regular intervals such as after every 8 or 16 symbols.
In 3FSK modulation, the linear convolutional encoder scheme
guarantees that the transmitted symbol sequence is dc-free,
facilitating symbol detection. However, Tx data scrambling is
recommended to limit the run length of zero symbols in the
transmit bit stream. Using 3FSK, the CDR data rate tolerance is
typically ±0.5%.
RECEIVER SETUP
Correlator Demodulator Setup
To enable the correlator for various modulation modes, refer to
Table 16.
Table 16. Enabling the Correlator Demodulator
Received Modulation
2FSK
3FSK
4FSK
To optimize receiver sensitivity, the correlator bandwidth must be
optimized for the specific deviation frequency and modulation
used by the transmitter. The discriminator bandwidth is
controlled by R4_DB[10:19] and is defined as
where:
DEMOD CLK is as defined in the Register 3—Transmit/Receive
Clock Register section.
K is set for each modulation mode according to the following:
For 2FSK,
DISCRIMINA
K
=
Round
⎛
⎜
⎜
⎝
100
TOR
f
×
DEV
10
_
BW
3
DEMOD_SCHEME (R4_DB[4:6])
001
010
011
⎞
⎟
⎟
⎠
=
(
DEMOD
400
×
CLK
10
3
×
K
)
Rev. 0 | Page 34 of 64
For 3FSK,
For 4FSK,
where:
Round is rounded to the nearest integer.
Round
31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3.
f
the frequency deviation used for the ±1 symbols (that is, the
inner frequency deviations).
To optimize the coefficients of the correlator, R4_DB7 and
R4_DB[8:9] must also be assigned. The value of these bits
depends on whether K is odd or even. These bits are assigned
according to Table 17 and Table 18.
Table 17. Assignment of Correlator K Value for 2FSK and 3FSK
K
Even
Even
Odd
Odd
Table 18. Assignment of Correlator K Value for 4FSK
K
Even
Odd
Linear Demodulator Setup
The linear demodulator can be used for 2FSK demodulation. To
enable the linear demodulator, set the DEMOD_SCHEME bits
(R4_DB[4:6]) to 000.
Post Demodulator Filter Setup
The 3 dB bandwidth of the post demodulator filter should be
set according to the received modulation type and data rate.
The bandwidth is controlled by R4_DB[20:29] and is given by
where f
demodulator filter.
Table 19. Post Demodulator Filter Bandwidth Settings for
2FSK/3FSK/4FSK Modulation Schemes
Received
Modulation
2FSK
3FSK
4FSK
DEV
is the transmit frequency deviation in Hz. For 4FSK, f
K
POST
K
4FSK
CUTOFF
=
=
Round
Round
K/2
Even
Odd
N/A
N/A
is rounded to the nearest of the following integers: 32,
_
is the target 3 dB bandwidth in Hz of the post
DEMOD
R4_DB7
0
1
4
FSK
⎛
⎜
⎜
⎝
100
2
(K + 1)/2
N/A
N/A
Even
Odd
⎛
⎜
⎜
⎝
×
100
4
×
f
×
_
DEV
Post Demodulator Filter Bandwidth,
f
0.75 × data rate
1 × data rate
1.6 × symbol rate (= 0.8 × data rate)
10
CUTOFF
×
f
BW
DEV
10
3
⎞
⎟
⎟
⎠
3
=
(Hz)
⎞
⎟
⎟
⎠
2
DEMOD
11
1
R4_DB7
0
0
1
×
π
R4_DB[8:9]
00
00
×
f
CUTOFF
CLK
R4_DB[8:9]
10
00
10
00
DEV
is