ADF7021-NBCPZ Analog Devices Inc, ADF7021-NBCPZ Datasheet - Page 35

• Manufacturer Part Number: ADF7021-NBCPZ
• Description: IC TXRX 80-650/842-916MHZ 48LFCS
• Manufacturer: Analog Devices Inc

Specifications of ADF7021-NBCPZ

• Frequency: 80MHz ~ 650MHz, 842MHz ~ 916MHz
• Data Rate - Maximum: 33kbps
• Modulation Or Protocol: 2-FSK, 3-FSK, 4-FSK, MSK
• Applications: Keyless Entery, Pagers, WMTS
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -130dBm
• Voltage - Supply: 2.3 V ~ 6 V
• Current - Receiving: 26mA
• Current - Transmitting: 32.3mA @ 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Receiving Current: 26.4mA
• Transmitting Current: 20.2mA
• Data Rate: 24Kbps
• Frequency Range: 80MHz To 916MHz
• Modulation Type: FSK, MSK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7021DBZ6 - BOARD EVAL ADF7021 608-614MHZEVAL-ADF7021DBZ5 - BOARD EVAL ADF7021EVAL-ADF7021DBZ3 - BOARD DAUGHTER FOR ADF7021EVAL-ADF7021DBZ2 - BOARD EVAL FOR ISM ADF7021
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3FSK Viterbi Detector Setup
The Viterbi detector can be used for 3FSK data detection. This
is activated by setting R13_DB11 to Logic 1.
The Viterbi path memory length is programmable in steps of 4,
6, 8, or 32 bits (VITERBI_PATH_MEMORY, R13_DB[13:14]).
The path memory length should be set equal to or greater than
the maximum number of consecutive 0s in the interleaved
transmit bit stream.
The Viterbi detector also uses threshold levels to implement the
maximum likelihood detection algorithm. These thresholds are
programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]).
These bits are assigned as follows:
where K is the value calculated for correlator discriminator
bandwidth.
Table 20. 3FSK CDR Settings
Parameter
PHASE_CORRECTION (R13_DB12)
3FSK_CDR_THRESHOLD (R13_DB[15:21])
3FSK_PREAMBLE_TIME_VALIDATE (R13_DB [22:25])
3FSK/4FSK_SLICER_THRESHOLD =
7 5
×
⎛
⎜ ⎜
⎝
Transmit F
requency
100
×
10
3
Deviation
×
K
⎞
⎟ ⎟
⎠
Recommended Setting
1
where K is the value calculated for correlator
discriminator bandwidth.
15
62
×
⎛
⎜
⎝
Transmit F
Rev. 0 | Page 35 of 64
requency
100
3FSK Threshold Detector Setup
To activate threshold detection of 3FSK, R13_DB11 should be
set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD bits
(R13_DB[4:10]) should be set as outlined in the 3FSK Viterbi
Detector Setup section.
3FSK CDR Setup
In 3FSK, a transmit preamble of at least 40 bits of continuous
1s is recommended to ensure a maximum number of symbol
transitions for the CDR to acquire lock.
The clock and data recovery for 3FSK requires a number of
parameters in Register 13 to be set (see Table 20).
4FSK Threshold Detector Setup
The threshold for the 4FSK detector is set using the
3FSK/4FSK_SLICER_THRESHOLD bits (R13_DB[4:10]).
The threshold should be set according to
where K is the value calculated for correlator discriminator
bandwidth.
×
10
3FSK/4FSK_SLICER_THRESHOLD =
Deviation
3
8 7
×
⎛
⎜ ⎜
⎝
4FSK
×
K
Outer
⎞
⎟
⎠
100
Purpose
Phase correction is on
Sets CDR decision threshold levels
Preamble detector time qualifier
Tx
×
10
Deviation
3
×
K
⎞
⎟ ⎟
⎠
ADF7021-N