AT86RF401U-XI Atmel, AT86RF401U-XI Datasheet - Page 48

• Manufacturer Part Number: AT86RF401U-XI
• Description: IC MICRO TX RF W/AVR 20-TSSOP
• Manufacturer: Atmel

Specifications of AT86RF401U-XI

• Frequency: 264MHz ~ 456MHz
• Applications: Garage Opener, RKE, Telemetry
• Modulation Or Protocol: ASK, OOK
• Data Rate - Maximum: 10 kbps
• Power - Output: 6dBm
• Current - Transmitting: 23.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 2KB Flash, 128 Byte EEPROM, 128Byte SRAM
• Voltage - Supply: 2 V ~ 5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: AT86RF401U

Table 22. Instruction Set (Continued)
48
Mnemonics
OUT
PUSH
POP
Bit and Bit-test Instructions
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
AT86RF401
Operands
P, Rr
Rr
Rd
P, b
P, b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Description
Out Port
Push Register on Stack
Pop Register from Stack
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit Load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watchdog Reset
Operation
P
STACK
Rd
I/O(P,b)
I/O(P,b)
Rd(n+1)
Rd(n)
Rd(0)
Rd(7)
Rd(n)
Rd(3...0)
SREG(s)
SREG(s)
T
Rd(b)
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
Not Implemented
(See specific description for WDR/timer)
1
0
Rr(b)
1
0
1
0
Rr
1
0
1
0
1
0
1
0
1
0
STACK
C, Rd(n+1)
C, Rd(n)
Rd(n+1), Rd(7)
Rd(n+1), n = 0...6
T
Rr
1
0
Rd(7...4), Rd(7...4)
Rd(n), Rd(0)
1
0
Rd(n+1), C
Rd(n), C
0
0
Rd(3...0)
Rd(7)
Rd(0)
Flags
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
1424F–RKE–12/03
#Clocks
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1