PN5331B3HN/C270,51 NXP Semiconductors, PN5331B3HN/C270,51 Datasheet - Page 22

• Manufacturer Part Number: PN5331B3HN/C270,51
• Description: IC NFC NEAR FIELD CTLR 40HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5331B3HN/C270,51

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443A, ISO1443B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287868518

NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
7.10.1 USB device controller
7.10.2 Features
7.10 USB interface (LPC2364/66/68 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and a number (127 maximum) of peripherals. The host controller allocates the USB
bandwidth to attached devices through a token based protocol. The bus supports hot
plugging, unplugging, and dynamic configuration of the devices. All transactions are
initiated by the host controller.
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory, and the
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate end point buffer memory. The status of a completed USB transfer or
error condition is indicated via status registers. An interrupt is also generated if enabled.
The DMA controller when enabled transfers data between the endpoint buffer and the
USB RAM.
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– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through standard RMII interface.
– PHY register access is available via the MIIM interface.
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB USB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, LPC2364/65/66/67/68 can enter one of the
reduced power modes and wake up on a USB activity.
Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Redundancy Check (CRC) for transmit.
receive filters or a magic frame detection filter.
Rev. 06 — 1 February 2010
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
© NXP B.V. 2010. All rights reserved.
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