MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet
MFRC53101T/0FE,112
Specifications of MFRC53101T/0FE,112
935269691112
MFRC531
MFRC53101TD
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MFRC53101T/0FE,112 Summary of contents
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... ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented Using this NXP Semiconductors’ device according to ISO/IEC 14443 B may infringe third party patent rights. The MFRC531 supports contactless communication using MIFARE higher baud rates (see Section 9.12 on page demodulation/decoding circuitry implementation for compatible transponder signals (see Section 9 ...
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... NXP Semiconductors The internal transmitter module designed for a proximity operating distance up to 100 mm without any additional active circuitry. A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility is supported (see 3. Features 3.1 General ...
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... NXP Semiconductors 4. Applications Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems 5. Quick reference data Table 1. Quick reference data Symbol Parameter T ambient temperature amb T storage temperature stg V digital supply voltage DDD V analog supply voltage DDA ...
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... NXP Semiconductors 7. Block diagram NWR NRD NCS ALE PARALLEL INTERFACE CONTROL (INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION) FIFO CONTROL 64-BYTE FIFO CONTROL REGISTER BANK EEPROM 32 × 16-BYTE ACCESS EEPROM CONTROL MASTER KEY BUFFER CYRPTO1 UNIT 32-BIT PSEUDO RANDOM GENERATOR AMPLITUDE RATING ...
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... NXP Semiconductors 8. Pinning information Fig 2. 8.1 Pin description Table 3. Pin description Pin Symbol Type 1 OSCIN I 2 IRQ O 3 MFIN I [2] 4 MFOUT O 5 TX1 O 6 TVDD P 7 TX2 O 8 TVSS G 9 NCS I [3] 10 NWR I R/NW I nWrite I [3] 11 NRD I NDS I nDStrb I 12 DVSS ...
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... NXP Semiconductors Table 3. Pin description …continued Pin Symbol Type [ I/O AD0 to AD7 I/O [3] 21 ALE nAStrb I NSS I [ nWait O MOSI [ SCK I 25 DVDD P 26 AVDD P 27 AUX O 28 AVSS VMID P 31 RSTPD I 32 OSCOUT O [1] Pin types Input Output, I/O = Input/Output Power and G = Ground. ...
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... NXP Semiconductors 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The MFRC531 supports direct interfacing to various 8-bit microprocessors. Alternatively, the MFRC531 can be connected to a PC’s Enhanced Parallel Port (EPP). the parallel interface signals supported by the MFRC531. Table 4. Bus control signals ...
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... NXP Semiconductors 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. MFRC531 pins ALE NRD NWR NCS 9.1.3.1 Separate read and write strobe address bus (A3 to An) ADDRESS DECODER address bus (A0 to A2) data bus (D0 to D7) HIGH Read strobe (NRD) Write strobe (NWR) Fig 3 ...
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... NXP Semiconductors 9.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER address bus (A0 to A2) data bus (D0 to D7) HIGH Data strobe (NDS) Read/Write (R/NW) Fig 4. Connection to microprocessor: common read and write strobes Refer to 9.1.3.3 Common read and write strobe: EPP with handshake Fig 5 ...
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... NXP Semiconductors Table 6. MFRC531 pins ALE NRD NWR NCS Figure 6 Fig 6. Remark: The SPI implementation for MFRC531 conforms to the SPI standard and ensures that the MFRC531 can only be addressed as a slave. 9.1.4.1 SPI read data The structure shown n-data bytes. The first byte sent defines both, the mode and the address. ...
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... NXP Semiconductors Table 8. Address (MOSI) byte 0 byte 1 to byte n reserved address address address address address address reserved byte [1] All reserved bits must be set to logic 0. 9.1.4.2 SPI write data The structure shown n-data bytes. The first byte sent defines both the mode and the address. ...
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... NXP Semiconductors 9.2 Memory organization of the EEPROM Table 11. Block Position MFRC531_34 Product data sheet PUBLIC EEPROM memory organization diagram Byte address Access Memory content Address 0 00h to 0Fh R 1 10h to 1Fh R/W 2 20h to 2Fh R/W 3 30h to 3Fh R/W 4 40h to 4Fh R/W 5 50h to 5Fh ...
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... NXP Semiconductors 9.2.1 Product information field (read only) Table 12. Byte Internal Table 13. Definition Byte Value [1] Byte 4 contains the current version number. 9.2.2 Register initialization files (read/write) Register initialization from address 10h to address 2Fh is performed automatically during the initializing phase (see initialization file. ...
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... NXP Semiconductors Remark: The following points apply to initialization: • the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. • make sure that all PreSetxx registers are not changed. • make sure that all register bits that are reserved are set to logic 0. ...
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... NXP Semiconductors Table 15. Shipment content of StartUp configuration file EEPROM Register Value Symbol byte address address 10h 10h 00h Page 11h 11h 58h TxControl 12h 12h 3Fh CwConductance 13h 13h 3Fh ModConductance 14h 14h 19h CoderControl 15h 15h 13h ModWidth 16h 16h ...
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... NXP Semiconductors 9.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see page 86). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. ...
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... NXP Semiconductors Remark possible to load data for other key formats into the EEPROM key storage location. However not possible to validate card authentication with data which will cause the LoadKeyE2 command (see 9.2.3.2 Storage of keys in the EEPROM The MFRC531 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No memory segmentation is used to mirror the 12-byte structure of key storage ...
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... NXP Semiconductors Table 17. Active command ReadE2 LoadKeyE2 LoadKey Authent1 Authent2 LoadConfig CalcCRC 9.3.2 Controlling the FIFO buffer In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit FIFOOvfl is cleared and the stored bytes are no longer accessible ...
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... NXP Semiconductors 9.3.4 FIFO buffer registers and flags Table 17 Table 18. Flags FIFOLength[6:0] FIFOOvfl FlushFIFO HiAlert HiAlertIEn HiAlertIRq LoAlert LoAlertIEn LoAlertIRq WaterLevel[5:0] 9.4 Interrupt request system The MFRC531 indicates interrupt events by setting the PrimaryStatus register bit IRq (see Section 10.5.1.4 “PrimaryStatus register” on page on pin IRQ can be used to interrupt the microprocessor using its interrupt handling capabilities ensuring efficient microprocessor software ...
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... NXP Semiconductors Table 19. Interrupt flag TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq 9.4.2 Interrupt request handling 9.4.2.1 Controlling interrupts and getting their status The MFRC531 informs the microprocessor about the interrupt request source by setting the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as source for an interrupt can be masked by the InterruptEn register interrupt enable bits ...
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... NXP Semiconductors 9.4.3 Configuration of pin IRQ The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be controlled using the following IRQPinConfig register bits. • bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq. • ...
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... NXP Semiconductors 9.5 Timer unit The timer derives its clock signal from the 13.56 MHz on-board chip clock. The microprocessor can use this timer to manage timing-relevant tasks. The timer unit can be used in one of the following configurations: • Timeout counter • WatchDog counter • ...
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... NXP Semiconductors 9.5.1 Timer unit implementation 9.5.1.1 Timer unit block diagram Figure 8 Fig 8. The timer unit is designed, so that events when combined with enabling flags start or stop the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received data with the timer unit. In addition, the first received bit is indicated by the TxBegin event. ...
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... NXP Semiconductors The timer is started immediately by loading a value from the TimerReload register into the counter module. This is activated by one of the following events: • transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1 • transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1 • ...
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... NXP Semiconductors 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt. ...
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... NXP Semiconductors 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. ...
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... NXP Semiconductors 9.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state ...
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... NXP Semiconductors 9.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the ...
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... NXP Semiconductors 9.8 Oscillator circuit Fig 10. Quartz clock connection The clock applied to the MFRC531 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry ...
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... NXP Semiconductors Table 25. TxControl register configuration TX2RFEn 9.9.2 Antenna operating distance versus power consumption Using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin TVDD possible to find the trade-off between maximum effective operating distance and power consumption. Different antenna matching circuits are described in the Application note “ ...
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... NXP Semiconductors 9.9.3.1 Source resistance table Table 26. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod MANT = Mantissa; EXP = Exponent. GsCfgCW, EXP , MANT GsCfgCW GsCfgMod EXP MANT GsCfgMod (decimal) (decimal) (decimal MFRC531_34 Product data sheet PUBLIC , R GsCfgCW, GsCfgCW S(ref) (Ω ...
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... NXP Semiconductors 9.9.3.2 Calculating the relative source resistance The reference source resistance ref The reference source resistance (R using ModConductance register’s GsCfgMod[5:0]. 9.9.3.3 Calculating the effective source resistance Wiring resistance (R resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The ...
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... NXP Semiconductors The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a phase-shift of 90° between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitized and then passed to the digital circuitry. Various adjustments can be made to obtain optimum performance for all processing units ...
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... NXP Semiconductors Automatic calibration can be set-up to execute at the end of each Transceive command if bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations except after the reset sequence. Automatic calibration can also be triggered by the software when bit ClkQCalib has a logic 0 to logic 1 transition. ...
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... NXP Semiconductors 9.10.2.3 Correlation circuitry The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure of the amplitude of the expected signal in the received signal. This is done for both, the Q and I-channels. The correlator provides two outputs for each of the two input channels, resulting in a total of four output signals ...
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... NXP Semiconductors Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The Manchester signal and the Manchester signal with subcarrier can only be accessed on pin MFOUT at 106 kBd based on ISO/IEC 14443 A. 9.11.1 Serial signal switch block diagram Figure 13 the serial signal switch enabling the MFRC531 to be used in different configurations. ...
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... NXP Semiconductors Table 28. See Table 93 on page 64 Number The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2. Table 29. See Table 93 on page 64 Number The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which routed to pin MFOUT ...
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... NXP Semiconductors Table 31. Register Analog circuitry settings ModulatorSource MFOUTSelect DecoderSource Digital circuitry settings ModulatorSource MFOUTSelect DecoderSource [1] The number column refers to the value in the number column of Two MFRC531 devices configured as described in other using pins MFOUT and MFIN. Remark: The active antenna concept can only be used at 106 kBd based on ISO/IEC 14443 A ...
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... TauD[1:0] TxCoding[2:0] As reference documentation, the international standard ISO/IEC 14443 Identification cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4 used. Remark: NXP Semiconductors does not offer a basic function library to design-in the ISO/IEC 14443 B protocol. MFRC531_34 Product data sheet PUBLIC describes the registers and flags covered by the ISO/IEC 14443 B ...
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... NXP Semiconductors 9.14 MIFARE authentication and Crypto1 The security algorithm used in the MIFARE products is called Crypto1 based on a proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards, knowledge of the key format is needed. The correct key must be available in the MFRC531 to enable successful card authentication and access to the card’s data stored in the EEPROM ...
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... NXP Semiconductors 9.14.2 Authentication procedure The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid authentication, the correct key has to be available in the key buffer of the MFRC531. This can be ensured as follows: 1. Load the internal key buffer by using the LoadKeyE2 (see or the LoadKey (see 2 ...
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... NXP Semiconductors Table 35. Multiplexed address bus type Paging mode Linear addressing 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers. the function of the Access column in the register tables. ...
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... NXP Semiconductors 10.3 Register overview Table 37. MFRC531 register overview Sub Register name address (Hex) Page 0: Command and status 00h Page 01h Command 02h FIFOData 03h PrimaryStatus 04h FIFOLength 05h SecondaryStatus 06h InterruptEn 07h InterruptRq Page 1: Control and status 08h Page 09h ...
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... NXP Semiconductors Table 37. MFRC531 register overview Sub Register name address (Hex) Page 4: RF Timing and channel redundancy 20h Page 21h RxWait 22h ChannelRedundancy 23h CRCPresetLSB 24h CRCPresetMSB 25h PreSet25 26h MFOUTSelect 27h PreSet27 Page 5: FIFO, timer and IRQ pin configuration 28h ...
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... NXP Semiconductors 10.4 MFRC531 register flags overview Table 38. Flag(s) AccessErr BitPhase[7:0] CharSpacing[2:0] ClkQ180Deg ClkQCalib ClkQDelay[4:0] CoderRate[2:0] CollErr CollLevel[3:0] CollPos[7:0] Command[5:0] CRC3309 CRC8 CRCErr CRCPresetLSB[7:0] CRCPresetMSB[7:0] CRCReady CRCResultMSB[7:0] CRCResultLSB[7:0] Crypto1On DecoderSource[1:0] E2Ready EOFWidth Err FIFOData[7:0] FIFOLength[6:0] FIFOOvfl FilterAmpDet FlushFIFO Force100ASK FramingErr Gain[1:0] ...
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... NXP Semiconductors Table 38. Flag(s) IFDetectBusy IRq IRQInv IRQPushPull ISO Selection[1:0] KeyErr LoAlert LoAlertIEn LoAlertIRq LPOff MFOUTSelect[2:0] MinLevel[3:0] ModemState[2:0] ModulatorSource[1:0] ModWidth[7:0] NoRxEGT NoRxEOF NoRxSOF NoTxEOF NoTxSOF PageSelect[2:0] ParityEn ParityErr ParityOdd PowerDown RcvClkSelI RxAlign[2:0] RxAutoPD RxCRCEn RxCoding RxFraming[1:0] RxIEn RxIRq RxLastBits[2:0] RxMultiple RxWait[7:0] ...
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... NXP Semiconductors Table 38. Flag(s) StandBy SubCPulses[2:0] TauB[1:0] TauD[1:0] TAutoRestart TestAnaOutSel[4:0] TestDigiSignalSel[6:0] TimerIEn TimerIRq TimerValue[7:0] TimeSlotPeriod[7:0] TimeSlotPeriodMSB TPreScaler[4:0] TReloadValue[7:0] TRunning TStartTxBegin TStartTxEnd TStartNow TStopRxBegin TStopRxEnd TStopNow TX1RFEn TX2Cw TX2Inv TX2RFEn TxCoding[2:0] TxCRCEn TxIEn TxIRq TxLastBits[2:0] UsePageSelect WaterLevel[5:0] ZeroAfterColl MFRC531_34 Product data sheet ...
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... NXP Semiconductors 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. Table 39. Bit Symbol Access Table 40. Bit 10.5.1.2 Command register Starts and stops the command execution. Table 41. Bit Symbol Access Table 42. Bit MFRC531_34 Product data sheet ...
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... NXP Semiconductors 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. Table 43. Bit Symbol Access Table 44. Bit 10.5.1.4 PrimaryStatus register Bits relating to receiver, transmitter and FIFO buffer status flags. Table 45. Bit Symbol Access Table 46. Bit Symbol ModemState[2:0] 3 IRq MFRC531_34 Product data sheet ...
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... NXP Semiconductors Table 46. Bit Symbol 2 Err 1 HiAlert 0 LoAlert 10.5.1.5 FIFOLength register Number of bytes in the FIFO buffer. Table 47. Bit Symbol Access Table 48. Bit Symbol FIFOLength[6:0] MFRC531_34 Product data sheet PUBLIC PrimaryStatus register bit descriptions Value Status FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation ...
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... NXP Semiconductors 10.5.1.6 SecondaryStatus register Various secondary status flags. Table 49. Bit Symbol Access Table 50. Bit Symbol 7 TRunning 6 E2Ready 5 CRCReady RxLastBits[2:0] 10.5.1.7 InterruptEn register Control bits to enable and disable passing of interrupt requests. Table 51. Bit Symbol Access Table 52. Bit Symbol 7 SetIEn TimerIEn 4 TxIEn ...
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... NXP Semiconductors 10.5.1.8 InterruptRq register Interrupt request flags. Table 53. Bit Symbol Access Table 54. Bit Symbol 7 SetIRq TimerIRq 4 TxIRq 3 RxIRq 2 IdleIRq 1 HiAlertIRq 0 LoAlertIRq [1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq. MFRC531_34 Product data sheet PUBLIC ...
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... NXP Semiconductors 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see 10.5.2.2 Control register Various control flags, for timer, power saving, etc. Table 55. Bit Symbol Access Table 56. Bit 10.5.2.3 ErrorFlag register Error flags show the error status of the last executed command. ...
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... NXP Semiconductors Table 58. Bit Symbol 5 AccessErr 4 FIFOOvfl 3 CRCErr 2 FramingErr 1 ParityErr 0 CollErr [1] Only valid for communication using ISO/IEC 14443 A. 10.5.2.4 CollPos register Bit position of the first bit-collision detected on the RF interface. Table 59. Bit Symbol Access Table 60. Bit Remark: A bit collision is not indicated in the CollPos register when using the ISO/IEC 14443 B protocol standard ...
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... NXP Semiconductors 10.5.2.5 TimerValue register Value of the timer. Table 61. Bit Symbol Access Table 62. Bit 10.5.2.6 CRCResultLSB register LSB of the CRC coprocessor register. Table 63. Bit Symbol Access Table 64. Bit 10.5.2.7 CRCResultMSB register MSB of the CRC coprocessor register. Table 65. Bit Symbol Access Table 66. ...
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... NXP Semiconductors 10.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 67. Bit Symbol Access Table 68. Bit Symbol RxAlign[2: TxLastBits[2:0] MFRC531_34 Product data sheet PUBLIC BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation RxAlign[2:0] R/W D BitFraming register bit descriptions ...
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... NXP Semiconductors 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see 10.5.3.2 TxControl register Controls the logical behavior of the antenna pin TX1 and TX2. Table 69. Bit Symbol Access Table 70. Bit MFRC531_34 Product data sheet PUBLIC Section 10.5.1.1 “Page register” on page ...
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... NXP Semiconductors 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. Table 71. Bit Symbol Access Table 72. Bit See Section 9.9.3 on page 30 10.5.3.4 ModConductance register Defines the driver output conductance. Table 73. Bit Symbol Access Table 74. Bit Remark: When Force100ASK = logic 1, the GsCfgMod[5:0] value has no effect. ...
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... NXP Semiconductors 10.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 75. Bit Symbol Access Table 76. Bit Symbol CoderRate[2: TxCoding[2:0] 10.5.3.6 ModWidth register Selects the pulse modulation width. Table 77. Bit Symbol Access Table 78. Bit 10.5.3.7 PreSet16 register Table 79. ...
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... NXP Semiconductors 10.5.3.8 TypeBFraming Defines the framing for ISO/IEC 14443 B communication. Table 80. Bit Symbol Access Table 81. Bit MFRC531_34 Product data sheet PUBLIC TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation 7 6 NoTxSOF NoTxEOF EOFWidth R/W R/W R/W TypeBFraming register bit descriptions ...
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... NXP Semiconductors 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see 10.5.4.2 RxControl1 register Controls receiver operation. Table 82. Bit Symbol Access Table 83. Bit Symbol SubCPulses[2: ISOSelection[1:0] 2 LPOff Gain[1:0] MFRC531_34 Product data sheet PUBLIC Section 10.5.1.1 “Page register” on page ...
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... NXP Semiconductors 10.5.4.3 DecoderControl register Controls decoder operation. Table 84. Bit Symbol Access Table 85. Bit Symbol RxMultiple 5 ZeroAfterColl RxFraming[1: RxCoding 10.5.4.4 BitPhase register Selects the bit-phase between transmitter and receiver clock. Table 86. Bit Symbol Access Table 87. Bit MFRC531_34 Product data sheet PUBLIC ...
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... NXP Semiconductors 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. Table 88. Bit Symbol Access Table 89. Bit 10.5.4.6 BPSKDemControl Controls BPSK demodulation. Table 90. Bit Symbol Access Table 91. Bit MFRC531_34 Product data sheet PUBLIC RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation ...
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... NXP Semiconductors 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. Table 92. Bit Symbol Access Table 93. Bit [1] I-clock and Q-clock are 90° phase-shifted from each other. 10.5.4.8 ClockQControl register Controls clock generation for the 90° phase-shifted Q-clock. ...
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... NXP Semiconductors 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. Table 96. Bit Symbol Access Table 97. Bit 10.5.5.3 ChannelRedundancy register Selects kind and mode of checking the data integrity on the RF channel. ...
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... NXP Semiconductors Table 99. Bit Symbol 1 ParityOdd 0 ParityEn [1] When used with ISO/IEC 14443 A, this bit must be set to logic 1. 10.5.5.4 CRCPresetLSB register LSB of the preset value for the CRC register. Table 100. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation ...
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... NXP Semiconductors 10.5.5.7 MFOUTSelect register Selects the internal signal applied to pin MFOUT. Table 105. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation Bit Symbol Access Table 106. MFOUTSelect register bit descriptions Bit Symbol 00000 MFOUTSelect[2:0] [1] Only valid for MIFARE and ISO/IEC 14443 A communication at 106 kBd. ...
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... NXP Semiconductors 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. Table 108. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation ...
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... NXP Semiconductors 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. Table 112. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit Symbol Access Table 113. TimerControl register bit descriptions Bit Symbol 0000 3 TStopRxEnd 2 TStopRxBegin 1 TStartTxEnd ...
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... NXP Semiconductors 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. Table 116. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit Symbol Access Table 117. IRQPinConfig register bit descriptions Bit 10.5.6.7 PreSet2E register Table 118. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation ...
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... NXP Semiconductors 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see 10.5.8.2 Reserved register 39h Table 121. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access Remark: This register is reserved for future use. ...
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... NXP Semiconductors 10.5.8.4 Reserved register 3Bh Table 124. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Table 125. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation ...
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... NXP Semiconductors 10.5.8.7 Reserved registers 3Eh, 3Fh Table 128. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit Symbol Access Remark: This register is reserved for future use. 11. MFRC531 command set MFRC531 operation is determined by an internal state machine capable of performing a command set ...
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... NXP Semiconductors Table 129. MFRC531 commands overview Command Value Action [1] Transceive 1Eh transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11 ...
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... NXP Semiconductors 11.1.1 Basic states 11.1.2 StartUp command 3Fh Table 130. StartUp command 3Fh Command StartUp Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data. It cannot be activated by the microprocessor but is automatically started after one of the following events: • ...
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... NXP Semiconductors 11.2 Commands for ISO/IEC 14443 A card communication The MFRC531 is a fully ISO/IEC 14443 A and ISO/IEC 14443 B compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE reader ICs. set for ISO/IEC 14443 A card communication and related communication protocols. ...
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... NXP Semiconductors 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bit; see Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is calculated and appended to the data stream ...
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... NXP Semiconductors Fig 16. Timing for transmitting byte oriented frames As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The MFRC531 appends this data to the data stream transmitted using the RF interface. If the internal accept further data signal is logic 0, the transmission terminates. All data written to the FIFO buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the FIFO buffer ...
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... NXP Semiconductors Figure 17 status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function. This function verifies FIFO empty for one bit duration before the last expected bit transmission ...
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... NXP Semiconductors If an EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). ...
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... NXP Semiconductors Table 135. Return values for bit-collision positions Collision in bit SOF Least Significant Bit (LSB) of the Least Significant Byte (LSByte) … Most Significant Bit (MSB) of the LSByte LSB of second byte … MSB of second byte LSB of third byte … Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur after bit-collisions in the data bits ...
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... NXP Semiconductors 11.2.3 Transceive command 1Eh Table 137. Transceive command 1Eh Command Value Transceive The Transceive command first executes the Transmit command (see page 76) and then starts the Receive command (see transmitted is sent using the FIFO buffer and all data received is written to the FIFO buffer. ...
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... NXP Semiconductors 11.2.5 Card communication state diagram Fig 18. Card communication state diagram MFRC531_34 Product data sheet PUBLIC COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE IDLE (000) FIFO not empty and command = command = Receive Transmit or Transceive TxSOF (001) SOF transmitted TxData (010) EOF transmitted and ...
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... NXP Semiconductors 11.3 EEPROM commands 11.3.1 WriteE2 command 01h Table 139. WriteE2 command 01h Command WriteE2 The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address. Any further bytes are interpreted as data bytes and are programmed into the EEPROM, starting from the given EEPROM start byte address ...
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... NXP Semiconductors 11.3.1.2 Timing diagram Figure 19 NWR write addr addr data byte 0 E2 LSB MSB WriteE2 command active EEPROM programming E2Ready TxIRq Fig 19. EEPROM programming timing diagram Assuming that the MFRC531 finds and reads byte 0 before the microprocessor is able to write byte which takes approximately 5 ...
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... NXP Semiconductors 11.3.2 ReadE2 command 03h Table 140. ReadE2 command 03h Command ReadE2 The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned. When all three argument bytes are available in the FIFO buffer, the specified number of data bytes are copied from the EEPROM into the FIFO buffer, starting from the given EEPROM starting byte address ...
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... NXP Semiconductors 11.4.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see EEPROM memory organization ...
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... NXP Semiconductors 11.5 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. Table 144. ErrorFlag register error flags overview ...
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... NXP Semiconductors The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in page 16. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer. ...
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... NXP Semiconductors 11.6.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the MFRC531 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0). ...
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... NXP Semiconductors 13.2 Current consumption Table 151. Current consumption Symbol Parameter I digital supply current DDD I analog supply current DDA I TVDD supply current DD(TVDD) 13.3 Pin characteristics 13.3.1 Input pin characteristics Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in Table 152 ...
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... NXP Semiconductors Pin RSTPD has Schmitt trigger CMOS characteristics. In addition internally filtered low-pass filter which causes a propagation delay on the reset signal. Table 154. RSTPD input pin characteristics Symbol Parameter The analog input pin RX has the input capacitance and input voltage range shown in Table 155 ...
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... NXP Semiconductors Table 157. Antenna driver output pin characteristics Symbol 13.4 AC electrical characteristics 13.4.1 Separate read/write strobe bus timing Table 158. Timing specification for separate read/write strobe Symbol t LHLL t AVLL t LLAX t LLRWL t SLRWL t RWHSH t RLDV t RHDZ t WLQV t WHDX t RWLRWH t AVRWL t WHAX ...
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... NXP Semiconductors ALE NCS NWR NRD Fig 20. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. The multiplexed address and data bus address lines (A0 to A2) must be connected as described in 13 ...
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... NXP Semiconductors Table 159. Common read/write strobe timing specification Symbol t AVDSL t RHAX t DSHDSL t WLDSL ALE NCS/NDS R/NW NRD Fig 21. Common read/write strobe timing diagram 13.4.3 EPP bus timing Table 160. Common read/write strobe timing specification for EPP Symbol t ASLASH t AVASH t ASHAV ...
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... NXP Semiconductors Table 160. Common read/write strobe timing specification for EPP Symbol t DSHDZ t DSLQV t DSHQX t DSHWX t DSLDSH t WLDSL t DSL-WAITH t DSH-WAITL Fig 22. Remark: cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in ...
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... NXP Semiconductors 13.4.4 SPI timing Table 161. SPI timing specification Symbol t SCKL t SCKH t DSHQX t DQXCH t h(SCKL-Q) t (SCKL-NSSH) SCK MOSI MISO NSS Fig 23. Timing diagram for SPI Remark: To send more bytes in one data stream the NSS signal must be LOW during the send process. To send more than one data stream the NSS signal must be HIGH between each data stream ...
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... NXP Semiconductors 14. EEPROM characteristics The EEPROM size is 32 × 16 × 4096 bit. Table 163. EEPROM characteristics Symbol N endu(W_ER) t ret a(W) 15. Application information 15.1 Typical application 15.1.1 Circuit diagram Figure 24 MFRC531: control lines MICROPROCESSOR Fig 24. Application example circuit diagram: directly matched antenna ...
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... NXP Semiconductors 15.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2n), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. Refer to the following application notes for more detailed information about designing and tuning an antenna. • ...
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... NXP Semiconductors 15.1.2.3 Receiver circuit The internal receiver of the MFRC531 makes use of both subcarrier load modulation side-bands. No external filtering is required recommended to use the internally generated VMID potential as the input potential for pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To provide a stable DC reference voltage, capacitor (C4) must be connected between VMID and ground ...
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... NXP Semiconductors 15.2 Test signals The MFRC531 allows different kinds of signal measurements. These measurements can be used to check the internally generated and received signals using the serial signal switch as described in In addition, the MFRC531 enables users to select between: • internal analog signals for measurement on pin AUX • ...
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... NXP Semiconductors (1) MFOUTSelect[2:0] = 001; serial data stream per division. (2) MFOUTSelect[2:0] = 010; serial data stream per division. (3) RFOut per division. Fig 25. TX control signals 15.2.1.2 RX control Figure 26 beginning of a card’s answer to a request signal. The RF signal shows the RF voltage measured directly on the antenna so that the card’s load modulation is visible ...
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... NXP Semiconductors (1) RFOut per division. (2) MFOUTSelect[2:0] = 011; Manchester with subcarrier per division. (3) MFOUTSelect[2:0] = 100; Manchester per division. Fig 26. RX control signals 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. ...
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... NXP Semiconductors Table 165. Analog test signal selection Value 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits. The signals selected by the TestDigiSignalSel[6:0] bits are shown in Table 166 ...
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... NXP Semiconductors Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit. Finally, the digital test signal s_data shows the received data. This is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. ...
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... NXP Semiconductors 16. Package outline SO32: plastic small outline package; 32 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 17. Abbreviations Table 167. Abbreviations and acronyms Acronym ASK BPSK CMOS CRC EOF EPP ETU FIFO HBM LSB MM MSB NRZ POR PCD PICC SOF SPI 18. References [1] Application note — MICORE reader IC family; Directly Matched Antenna Design. [2] Application note — MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas. ...
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... Legal texts have been adapted to the new company name where appropriate • The symbols for electrical characteristics and their parameters have been updated to meet the NXP Semiconductors’ guidelines • A number of inconsistencies in pin, register and bit names have been eliminated from the data sheet • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 21. Contact information For more information, please visit: For sales office addresses, please send an email to: MFRC531_34 Product data sheet PUBLIC http://www.nxp.com salesaddresses@nxp.com Rev. 3.4 — 26 January 2010 056634 MFRC531 ISO/IEC 14443 reader IC © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 22. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Supported microprocessor and EPP interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 6. SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10 Table 7. SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 8. SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11 Table 9. ...
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... NXP Semiconductors Table 70. TxControl register bit descriptions . . . . . . . . . .57 Table 71. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . .58 Table 72. CwConductance register bit descriptions . . . .58 Table 73. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . .58 Table 74. ModConductance register bit descriptions . . . .58 Table 75 ...
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... NXP Semiconductors Table 136. Communication error table . . . . . . . . . . . . . . .81 Table 137. Transceive command 1Eh . . . . . . . . . . . . . . .82 Table 138. Meaning of ModemState . . . . . . . . . . . . . . . . .82 Table 139. WriteE2 command 01h . . . . . . . . . . . . . . . . . .84 Table 140. ReadE2 command 03h . . . . . . . . . . . . . . . . . .86 Table 141. LoadConfig command 07h . . . . . . . . . . . . . . .86 Table 142. CalcCRC command 12h . . . . . . . . . . . . . . . . .87 Table 143. CRC coprocessor parameters . . . . . . . . . . . .87 Table 144 ...
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... NXP Semiconductors 24. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 8.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Functional description . . . . . . . . . . . . . . . . . . . 7 9.1 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 Automatic microprocessor interface detection ...
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... NXP Semiconductors 9.14.2 Authentication procedure . . . . . . . . . . . . . . . . 41 10 MFRC531 registers . . . . . . . . . . . . . . . . . . . . . 41 10.1 Register addressing modes . . . . . . . . . . . . . . 41 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 41 10.1.2 Dedicated address bus . . . . . . . . . . . . . . . . . . 41 10.1.3 Multiplexed address bus . . . . . . . . . . . . . . . . . 41 10.2 Register bit behavior 10.3 Register overview . . . . . . . . . . . . . . . . . . . . . . 43 10.4 MFRC531 register flags overview 10.5 Register descriptions . . . . . . . . . . . . . . . . . . . 48 10.5.1 Page 0: Command and status . . . . . . . . . . . . 48 10 ...
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... NXP Semiconductors 11.3.1 WriteE2 command 01h . . . . . . . . . . . . . . . . . . 84 11.3.1.1 Programming process . . . . . . . . . . . . . . . . . . 84 11.3.1.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.1.3 WriteE2 command error flags . . . . . . . . . . . . . 85 11.3.2 ReadE2 command 03h . . . . . . . . . . . . . . . . . . 86 11.3.2.1 ReadE2 command error flags 11.4 Diverse commands . . . . . . . . . . . . . . . . . . . . . 86 11.4.1 LoadConfig command 07h . . . . . . . . . . . . . . . 86 11.4.1.1 Register assignment . . . . . . . . . . . . . . . . . . . . 86 11.4.1.2 Relevant LoadConfig command error flags . . 87 11 ...