MFRC53101T/0FE,112 NXP Semiconductors, MFRC53101T/0FE,112 Datasheet - Page 29

IC MIFARE HS READER 32-SOIC

MFRC53101T/0FE,112

Manufacturer Part Number
MFRC53101T/0FE,112
Description
IC MIFARE HS READER 32-SOIC
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Datasheets

Specifications of MFRC53101T/0FE,112

Rf Type
Read Only
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B, ISO15693
Package / Case
32-SOIC (0.300", 7.50mm Width)
Product
RFID Readers
Operating Temperature Range
- 25 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2224-5
935269691112
MFRC531
MFRC53101TD

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MFRC53101T/0FE,112
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
MFRC531_34
Product data sheet
PUBLIC
9.9.1 Configuring pins TX1 and TX2
9.8 Oscillator circuit
9.9 Transmitter pins TX1 and TX2
The clock applied to the MFRC531 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified. It must meet the specifications described in
page
Remark: We do not recommend using an external clock source.
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly, using minimal passive
components for matching and filtering (see
output circuitry is designed with a very low-impedance source resistance. The TxControl
register is used to control the TX1 and TX2 signals.
TX1 pin configurations are described in
Table 24.
TX2 pin configurations are described in
TxControl register configuration
TX1RFEn
Fig 10. Quartz clock connection
97.
0
1
1
1
1
Pin TX1 configurations
FORCE100ASK
Rev. 3.4 — 26 January 2010
X
0
0
1
1
056634
15 pF
OSCOUT
MFRC531
Envelope TX1 signal
13.56 MHz
Table
Table
X
Section 15.1 on page
0
1
0
1
OSCIN
24.
25.
LOW (GND)
13.56 MHz carrier frequency modulated
13.56 MHz carrier frequency
LOW
13.56 MHz energy carrier
001aal224
15 pF
ISO/IEC 14443 reader IC
98). To enable this, the
MFRC531
Section 13.4.5 on
© NXP B.V. 2010. All rights reserved.
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