PIC18F86J72-I/PT Microchip Technology, PIC18F86J72-I/PT Datasheet - Page 271

• Manufacturer Part Number: PIC18F86J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 12MIPS
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

20.5
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA2<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK2 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
20.5.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG2 and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 20-8:
 2010 Microchip Technology Inc.
INTCON
PIR3
PIE3
IPR3
RCSTA2
TXREG2
TXSTA2
SPBRG2
LATG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG2
register.
Flag bit, TX2IF, will not be set.
When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit, TX2IF, will now be
set.
If enable bit, TX2IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
AUSART Synchronous Slave Mode
AUSART SYNCHRONOUS
SLAVE TRANSMIT
AUSART Transmit Register
AUSART Baud Rate Generator Register
GIE/GIEH PEIE/GIEL
CSRC
U2OD
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
—
—
LCDIF
LCDIE
LCDIP
U1OD
Bit 6
RX9
TX9
TMR0IE
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
—
Preliminary
INT0IE
LATG4
TX2IE
TX2IP
CREN
SYNC
TX2IF
Bit 4
PIC18F87J72 FAMILY
CTMUIF
CTMUIE
CTMUIP
ADDEN
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
LATG3
RBIE
Bit 3
—
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
Clear bits, CREN and SREN.
If interrupts are desired, set enable bit, TX2IE.
If 9-bit transmission is desired, set bit, TX9.
Enable the transmission by setting enable bit,
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Start transmission by loading data to the
TXREG2 register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP2IF
CCP2IE
CCP2IP
LATG2
BRGH
FERR
Bit 2
CCP1IF
CCP1IE
CCP1IP
INT0IF
LATG1
OERR
TRMT
Bit 1
RTCCIF
RTCCIE
RTCCIP
LATG0
RX9D
TX9D
RBIF
DS39979A-page 271
Bit 0
on Page
Values
Reset
49
52
52
52
54
54
54
52
54