PIC18F86J72-I/PT Microchip Technology, PIC18F86J72-I/PT Datasheet - Page 360
PIC18F86J72-I/PT
Manufacturer Part Number
PIC18F86J72-I/PT
Description
IC PIC MCU 8BIT 14KB FLSH 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F86J72-IPT.pdf
(480 pages)
Specifications of PIC18F86J72-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
80-TQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, SPI, I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
14
Controller Family/series
PIC18F
No. Of I/o's
51
Ram Memory Size
3923Byte
Cpu Speed
12MIPS
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J72-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87J72 FAMILY
MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39979A-page 360
Q Cycle Activity:
After Instruction
Decode
W
Q1
=
Move Literal to W
MOVLW k
0 k 255
k W
None
The eight-bit literal ‘k’ is loaded into W.
1
1
literal ‘k’
MOVLW
Read
0000
Q2
5Ah
1110
5Ah
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
Preliminary
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
Move data from W to register ‘f’.
1
Move W to f
MOVWF
0 f 255
a [0,1]
(W) f
None
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 27.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
MOVWF
Read
0110
Q2
4Fh
FFh
4Fh
4Fh
2010 Microchip Technology Inc.
REG, 0
f {,a}
111a
Process
Data
Q3
ffff
register ‘f’
Write
Q4
ffff
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