PIC18F86J72-I/PT Microchip Technology, PIC18F86J72-I/PT Datasheet - Page 380
PIC18F86J72-I/PT
Manufacturer Part Number
PIC18F86J72-I/PT
Description
IC PIC MCU 8BIT 14KB FLSH 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F86J72-IPT.pdf
(480 pages)
Specifications of PIC18F86J72-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
80-TQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, SPI, I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
14
Controller Family/series
PIC18F
No. Of I/o's
51
Ram Memory Size
3923Byte
Cpu Speed
12MIPS
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J72-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87J72 FAMILY
SUBFSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39979A-page 380
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2
FSR2
Q1
=
=
register ‘f’
Subtract Literal from FSR
SUBFSR f, k
0 k 63
f [ 0, 1, 2 ]
FSRf – k FSRf
None
The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
1
1
SUBFSR 2, 23h
Read
1110
Q2
03FFh
03DCh
1001
Process
Data
Q3
ffkk
destination
Write to
kkkk
Q4
Preliminary
SUBULNK
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Operation
Decode
FSR2
PC
FSR2
PC
No
Q1
Subtract Literal from FSR2 and Return
SUBULNK k
0 k 63
FSR2 – k FSR2,
(TOS) PC
None
The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case
of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
1
2
=
=
=
=
1110
register ‘f’
Operation
SUBULNK 23h
Read
No
Q2
03FFh
0100h
03DCh
(TOS)
2010 Microchip Technology Inc.
1001
Operation
Process
Data
No
Q3
11kk
destination
Operation
Write to
kkkk
No
Q4
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