PIC18F86J72-I/PT Microchip Technology, PIC18F86J72-I/PT Datasheet - Page 325
PIC18F86J72-I/PT
Manufacturer Part Number
PIC18F86J72-I/PT
Description
IC PIC MCU 8BIT 14KB FLSH 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F86J72-IPT.pdf
(480 pages)
Specifications of PIC18F86J72-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
80-TQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
51
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, SPI, I2C
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
51
Number Of Timers
4
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
14
Controller Family/series
PIC18F
No. Of I/o's
51
Ram Memory Size
3923Byte
Cpu Speed
12MIPS
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J72-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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26.2
For PIC18F87J72 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 26-1:
2010 Microchip Technology Inc.
All Device Resets
INTRC Oscillator
WDTPS<3:0>
Watchdog Timer (WDT)
SWDTEN
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
128
INTRC Control
4
Programmable Postscaler
Preliminary
1:1 to 1:32,768
PIC18F87J72 FAMILY
26.2.1
The WDTCON register (Register 26-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
WDT
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
DS39979A-page 325
Wake-up from
Power-Managed
Modes
WDT
Reset
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