PIC18F86J72-I/PT Microchip Technology, PIC18F86J72-I/PT Datasheet - Page 382

• Manufacturer Part Number: PIC18F86J72-I/PT
• Description: IC PIC MCU 8BIT 14KB FLSH 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J72-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, USART, SPI, I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14
• Controller Family/series: PIC18F
• No. Of I/o's: 51
• Ram Memory Size: 3923Byte
• Cpu Speed: 12MIPS
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F87J72 FAMILY
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39979A-page 382
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
OFST
FSR2
Contents
of 0A2Ch
W
Contents
of 0A2Ch
Q1
(W) + ((FSR2) + k)  dest
Read ‘k’
ADDWF
ADD W to Indexed
(Indexed Literal Offset mode)
ADDWF
0  k  95
d  [0,1]
N, OV, C, DC, Z
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
1
1
0010
Q2
=
=
=
=
=
=
[OFST] ,0
[k] {,d}
01d0
17h
2Ch
0A00h
20h
37h
20h
Process
Data
Q3
kkkk
destination
Write to
Q4
kkkk
Preliminary
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Decode
FLAG_OFST
FSR2
Contents
of 0A0Ah
Contents
of 0A0Ah
OFST
FSR2
Contents
of 0A2Ch
Contents
of 0A2Ch
Q1
Q1
register ‘f’
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0  f  95
0  b  7
1  ((FSR2) + k)<b>
None
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
BSF
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0  k  95
FFh  ((FSR2) + k)
None
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
1
1
Read ‘k’
SETF
Read
1000
0110
Q2
Q2
=
=
=
=
 2010 Microchip Technology Inc.
=
=
=
=
2Ch
0A00h
00h
FFh
[FLAG_OFST], 7
[OFST]
bbb0
1000
Process
0Ah
0A00h
55h
D5h
Process
Data
Data
Q3
Q3
kkkk
kkkk
destination
Write to
register
Write
Q4
Q4
kkkk
kkkk