ATMEGA64A-MN Atmel, ATMEGA64A-MN Datasheet - Page 134

• Manufacturer Part Number: ATMEGA64A-MN
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8160C–AVR–07/09
Table 15-3
PWM mode
Table 15-3.
Note:
Table 15-3
correct and frequency correct PWM mode.
Table 15-4.
Note:
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes.
COMnA1/
COMnB1/
COMnA1/
COMnB1/
COMnC0
COMnC1
0
0
1
1
0
0
1
1
1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
1. A special case occurs when OCRnA/OCRnB/OC
COMnA1/COMnB1/COMnC1 is set. In this case the Compare Match is ignored, but the set or
clear is done at BOTTOM.
COMnA1/COMnB1/COMnC1 is set.
details.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
Compare Output Mode, Fast PWM
Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
COMnA0/
COMnB0/
COMnA0/
COMnB0/
COMnC0
COMnC0
(1)
0
1
0
1
0
1
0
1
Table
Description
Normal port operation, OCnA/OCnB/OCnC disconnected.
WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB/OCnC
disconnected (normal port operation).
For all other WGMn settings, normal port operation,
OCnA/OCnB/OCnC disconnected.
Clear OCnA/OCnB/OCnC on Compare Match, set
OCnA/OCnB/OCnC at BOTTOM (non-inverting mode).
Set OCnA/OCnB/OCnC on Compare Match, clear
OCnA/OCnB/OCnC at BOTTOM (inverting mode).
Description
Normal port operation, OCnA/OCnB/OCnC disconnected.
WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB/OCnC
disconnected (normal port operation).
Forr all other WGMn settings, normal port operation,
OCnA/OCnB/OCnC disconnected.
Clear OCnA/OCnB/OCnC on Compare Match when up-counting. Set
OCnA/OCnB/OCnC on Compare Match when downcounting.
Set OCnA/OCnB/OCnC on Compare Match when up-counting. Clear
OCnA/OCnB/OCnC on Compare Match when downcounting.
See “Fast PWM Mode” on page 124.
15-5. Modes of operation supported by the Timer/Counter
(See “Modes of Operation” on page
See “Phase Correct PWM Mode” on page 126.
(1)
Rn
C equals TOP and
for more details.
ATmega64A
123.)
for more
134